Author: RakshithM_16 Version: **
Frequency of clock can be set by one of the two methods as follows:
1. Auto mode: Enter the frequency directly in the Frequency tab as shown in Figure 1.
Figure 1. Setting frequency of clock in auto mode
2. Manual mode: Use fractional dividers and set the divider values as shown in Figure 2.
Figure 2. Setting frequency of clock in manual mode
In auto mode, setting a frequency which is derived by using integer divider values will not cause an issue. However, setting a frequency which is derived by using a fractional divider value is set incorrectly independent of the Use fractional divider checkbox. A frequency value which is the closest frequency obtained without using fractional dividers is set.
For example, if the source clock frequency is 50 MHz, a frequency of 25 MHz is set correctly, as it can be derived using an integer divider, 2.
However, choosing a frequency of 32 MHz will set it again to 25 MHz (50 MHz / 2) because it is the closest frequency obtained without using fractional dividers (25 MHz (50 MHz / 2) is closer compared to 50 MHz (50 MHz / 1) and 16.67 MHz (50 MHz / 3)).
This happens because fractional dividers are not used when auto mode is chosen.
To use fractional dividers, use manual mode and set the divider and fractional divider values.
Set the divider value to the integer value which gives the closest frequency greater than or equal to the required frequency. For example, if 32 MHz is the required frequency and 50 MHz is the source frequency, then the divider value to be set is 1.
Set the fractional divider value according to the equation:
Therefore, in the case of 32 MHz, the fractional divider value is equal to 18.
For more information on clock dividers and fractional dividers, see the device-specific Architecture TRM.
For PSoC 4 devices, the option to set divider is not available if the Source is set to <Auto> as shown in Figure 3.
Figure 3. Clock settings when Source is set to <Auto>
Select the appropriate source clock. The option to set divider and fractional divider values are now available as shown in Figure 4.
Figure 4. Clock settings when Source is assigned to an appropriate clock