Author: EktaN_26 Version: **
PSoC 4100S Plus devices always start up using the IMO; the ExtClk can only be enabled in the user application during runtime. Also, the device cannot be started from reset which is clocked by EXTCLK.
Do the following to switch to EXTCLK:
- Open the project In PSoC Creator.
- In the project, click the Clocks tab under Design Wide Resources and click Edit Clock.
- Under High Frequency Clocks tab, enable both ExtClk and IMO.
- Set the frequency for both IMO and ExtClk.
- Set the source of the HFClk to IMO as shown in Figure 1 below. P0 is the default pin used for providing input to the external clock.
Figure 1: Clock Configuration
You can switch to the external clock during run time with the CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_EXTCLK) API function. This will switch the input of the HFClk from IMO to ExtClk.
For PSoC 4100S Plus devices, you must manually enable the srss.ext_clk HSIOM connection for P0 pin using the following code in main.c:
CY_SET_REG32((void *)(CYREG_HSIOM_PORT_SEL0), (CYVAL_HSIOM_IO0_SEL_ACT_0 << (6 * 4))); /* HSIOM_IO0_SEL_ACT_0 */
CY_SET_REG32((void *)(CYREG_GPIO_PRT0_PC), (CY_SYS_PINS_DM_DIG_HIZ << (6 * 3))); /* High Impedance Digital */
/* 6 is a pin number, 3 and 4 are bitfield widths */
/* Perform the desired function */
Note: The new clock source must be running and stable before calling this function. If the SysClk frequency increases during device operation, call CySysFlashSetWaitCycles() with the appropriate parameter to adjust the number of clock cycles the cache will wait before sampling data comes back from the flash. If the SysClk frequency decreases, call CySysFlashSetWaitCycles() to improve the CPU performance. See CySysFlashSetWaitCycles() description in PSoC 4 System Reference Guide for more information.