Resets During Flash Row Write in PSoC 3 / PSoC 4 / PSoC 5LP / PSoC 6 MCU Designs – KBA229051

Version 3

    Author: GeonaM_26         Version: **


    Translation - Japanese: PSoC 3 / PSoC 4 / PSoC 5LP / PSoC 6 MCUデザインでのフラッシュ行(row)の書き込み中のリセットについて- KBA229051 - Community Translated (JA)


    During flash write, the device power supply must be stable and device must not be reset. Otherwise, flash operations will be interrupted and cannot be relieved on to have completed. Refer to Flash AC Specifications table in the respective device datasheet for flash row write time.


    Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdog resets. If you are using flash writes, Emulated EEPROM component, Bootloader, or Device Firmware Update SDK in your designs, ensure that these resets are not inadvertently activated. Refer to the respective device’s Hardware Design Considerations Application Note for recommendations on stable power supply designs.


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