Author: BragadeeshV_41 Version: **
Translation - Japanese: クロックストレッチ機能が無効になっている場合のPSoC 4 EZI2Cクロックストレッチ - KBA228299 - Community Translated (JA)
The EZI2C Component will perform clock stretching even if the clock stretching feature is disabled in the Component window. Whenever the PSoC slave device finds a valid start condition on the bus, an interrupt is generated. The slave ISR should be executed which updates the Tx FIFO contents. This means that the old contents are removed, and the new contents are copied from the slave buffer into the Tx FIFO. If the master tries to read the Tx FIFO even before the slave places the first byte of data into the Tx FIFO, the slave will try to stretch the clock until the data is available.
The maximum delay between the moment the start condition was detected and the EZI2C ISR is serviced is called maximum interrupt latency. When the clock stretching feature is disabled, it poses a higher timing constraint on interrupt latency.
Newer versions of the EZI2C Component have an optimized interrupt handler so that it can load the first byte of the Tx FIFO before the master attempts to read the data from the Tx FIFO. If the interrupt latency in your design is greater than the maximum interrupt latency as defined in the Component datasheet, you might find erroneous slave performances such as clock stretching. This becomes a problem when clock stretching is unacceptable for the master.
In most designs, a master read operation is performed immediately after a master write operation calls repeated start conditions’; that is, instead of a stop condition after the write operation, a restart condition is issued by the master to begin the read operation. In such cases, the maximum interrupt latency time is still reduced. See the EZI2C Component datasheet for more information on the maximum interrupt latency.
To understand this issue, consider the following example:
An EZI2C Component is set up to work at 400 kHz with clock stretching disabled using a PSoC 4000 device. The CPU clock is at 12 MHz. A timer is used to generate an interrupt at every 1 ms with the priority higher than that of the EZI2C Component that is used to simulate the issue as shown in Figure 1 and Figure 2:
Figure 1. Top design
Figure 2. Interrupt priority of timer is set higher than EZI2C
It can be seen from Figure 3 that the EZI2C slave attempts to stretch the clock even if the EZI2C clock stretching option is disabled in the Component configuration window.
Figure 3. Clock stretching by EZI2C slave
There are several ways you can prevent this:
1. Use the highest clock speed possible so that you can have the minimum interrupt latency.
2. Have the EZI2C ISR with the highest priority (as required by the design) so that the EZI2C interrupt will not be preempted by a high-priority interrupt, which might exceed the maximum slave latency.
Refer to AN90799 PSoC 4 Interrupts for more information on interrupts in PSoC 4.
3. Use optimization options of the compiler so that it reduces the number of instructions to execute in the EZ I2C slave interrupt service routine.
4. Calculate the duration of each critical section in your design and compare it with the EZ I2C maximum interrupt latency to ensure that the design meets the maximum interrupt latency criteria.
5. Use critical section (disable interrupts) for updating the EZI2C buffer.
Refer to PSoC 4 System Reference Guide for more information on critical sections.
Reference: NXP I2C specification