What are the manual settings required to generate a clock of 48 MHz and accuracy of +/-0.25% for USB operation using FLL, for PSoC 6 MCU?
Do the following:
- In the Workspace Explorer, click on the Clock section under Design Wide Resource.
Figure 1. Step 1 and Step 2
2. Under the Clocks tab, click Edit Clock as shown in Figure 1. The Configure System Clocks window appears.
3. On the Configure System Clock window, click on the FLL/PLL tab. In PathMux0, select the source for FLL as IMO (8 MHz), and then click on the check box for FLL to enable it.
Figure 2. Step 3 and Step 4
4. Click on the ellipsis (‘…’) to configure the FLL.
5. In the Configure FLL dialogue, enable the manual section and make the following settings:
Figure 3. Step 5
- Multiplier(1-262143): 1728
- Reference(1-8191): 144
- Clock tolerance(0-511): 2
After these settings are made, the output of FLL will be a 48 MHz clock with an accuracy of +/-0.2% .
Note: To set the clock frequency to 96 MHz (with an accuracy of +/- 0.2%), set the parameters as follows:
- Multiplier (1-262143): 1728
- Reference (1-8191): 72
- Clock tolerance (0-511): 2
6. For PSoC 6 MCU, CLK_HF is the root clock for USB communication. Under the High Frequency Clock, select Path0 (48MHz), This means that the FLL clock is configured as the source of Clk_HF3 as shown in Figure 4.
Figure 4. Step 6
For more details on calculation of the parameters in the manual settings, see the “Configure FLL” section of the PSoC 6 Architecture TRM .