PCM/I2S Clock Setting in CYW20706 for Audio Applications - KBA228409

Version 7

    Author: LinglingG_46          Version: **


    Translation - Japanese: オーディオ アプリケーション向けのCYW20706のPCM/I2Sクロック設定– KBA228409 - Community Translated (JA)


    The I2S or PCM clock of CYW20706 cannot be set by the audio application. The audio firmware/hardware control the clock setting based on the current audio stream bit depth, sample rate, number of channels, etc.



    On the CYW20706 device, I2S is used for routing audio samples while using the A2DP profile. The direction of the audio samples depends on the A2DP role of the device. If the CYW20706 device is configured as a source, audio samples are received from a hardware codec over I2S. If configured as a sink, audio samples are transmitted from CYW20706 to the hardware codec.


    In A2DP applications, the audio data is routed over I2S by default or when the route is configured as AUDIO_ROUTE_I2S. CYW20706 can be configured as the I2S master by setting the is_master flag to TRUE. CYW20706 will then generate the bit clock (SCK) based on the sampling frequency negotiated over the A2DP profile.

    For example, if the CYW20706 device negotiates a sampling frequency of 44.1 kHz with the peer Bluetooth device during codec negotiation, the I2S clock frequency will be set to 44.1 kHz by the internal libraries. The bit depth or word length is set to 16, i.e., the frame length is fixed to 32 and cannot be modified. The I2S clock in the master mode can either be


    • 44.1 kHz × 32 bits per frame = 1411.2 kHz • 48 kHz × 32 bits per frame = 1536 kH
    • In slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

    In slave mode, any clock rate is supported up to a maximum of 3.072 MHz


    Note: If CYW20706 is an A2DP source, you can set the sampling frequency in the application firmware. For example, check in ‘watch’ demo available in WICED Studio SDK: av_app_cb.audio_sf = 'desired sampling frequency'; 



    PCM is a standard method used to digitize audio (particularly voice) for transmission over digital communication channels. CYW20706 includes a PCM interface that can connect to linear PCM codec devices either in master or in slave mode. The PCM interface is used for full duplex bidirectional transfer of 8K or 16K voice samples while using the HFP profile.


    CYW20706 uses 13 bits of the 16 bits in each PCM frame. The remaining three bits need to be ignored at the input device and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left-justified, filled with 0s, and clocked MSB first.

    The PCM clock setting will be done internally based on the sample rate in SCO settings.

    If wide band speech (WBS) is enabled, CYW20706 will use 16K sample rate; otherwise 8K.

    Check WICED_BT_HFP_HFP_CODEC_SET_EVT to determine whether WBS is enabled.


    Thus, the PCM clock can either be one of the following:

    • 8 kHz × 16 bits × 2 (channel) = 256 kHz (For narrow band speech)
    • 16 kHz × 16 bits × 2 (channel) = 512 kHz (For wide band speech)

    WICED Stack manages this. You just need to enable or disable WBS in the application project.