Volatile and Non-Volatile Registers in Serial Flash Devices – KBA228310

Version: **

 

Question:

How do Cypress Serial Flash devices use volatile and non-volatile versions of status and configuration registers for its operation?

 

Answer:

Some of the Cypress serial NOR flash devices have separate volatile and non-volatile status and configuration registers, which are small groups of memory cells used to configure how the memory device operates, or to indicate the status of device operations. It could be a mixture of volatile, nonvolatile, read-only, or OTP bits in the same register space.

 

When a nonvolatile version of any register is updated, the new values are automatically updated in the corresponding volatile registers. There is an immediate feed through from nonvolatile registers to volatile counterparts. This behavior is irrespective of the command being used to update the nonvolatile register values. Nonvolatile registers are used only for initializing volatile registers after Power On Reset (POR), hardware reset, or software reset. The flash device will always use the value of the volatile registers during its operation. Nonvolatile bits have the same cycling (erase and program) endurance as the main flash array. So, it is strongly suggested not to write the nonvolatile register bits on every system boot. Special attention must be given when writing the nonvolatile registers that there is a stable power supply with no disruption. This will guarantee that the correct data is written to the register.

 

Volatile register bits can be modified to different values from their counterpart nonvolatile register bits at any time. When volatile register bits are written, only the volatile version of the register has the appropriate bits updated. Their counterpart nonvolatile register bits remain unchanged. On Power On Reset, hardware reset, or software reset, volatile register bits will be reloaded from their nonvolatile counterpart.

 

In the case of OTP bits, when a nonvolatile OTP bit is updated once, the volatile counterpart of that bit gets updated with the new value immediately. Upon trying to update the nonvolatile OTP bit again, the value of this bit does not get updated (as expected), and the value of the volatile counterpart also remains same, i.e., the volatile counterpart does not get updated either.

 

However, having said that, it should be kept in mind that even if the nonvolatile OTP bit has been programmed once, and provided that the volatile counterpart of such a bit is not volatile read-only in nature, the volatile counterpart can be changed to a value different from the nonvolatile OTP bit; the device operation will be governed by the value of the volatile register bits.

To understand this with the help of an example, let us look at how block protection will work in S25FS512S device. The following tables show the Status Register-1 bits.

Status Register-1 Non Volatile (SR1NV)

Bits

7

6

5

4

3

2

1

0

Field Name

SRWD_NV

P_ERR_D

E_ERR_D

BP_NV2

BP_NV1

BP_NV0

WEL_D

WIP_D

 

Status Register-1 Volatile (SR1V)

Bits

7

6

5

4

3

2

1

0

Field Name

SRWD

P_ERR

E_ERR

BP2

BP1

BP0

WEL

WIP

The BP_NV [2-0] of SR1NV and BP [2-0] bits of SR1V control the protection of the flash array. The size of the range of memory that these bit configurations will protect are the same for both set of bits. Let us say, we program BP_NV [2-0] bits with [1-1-1] and BP [2-0] bits with [1-1-0].

 

BP_NV2

BP_NV1

BP_NV0

Protected Fraction of Memory

 

BP2

BP1

BP0

Protected Fraction of Memory

1

1

1

All Sectors

 

1

1

0

Upper Half

The BP_NV bit configuration will protect the entire flash array, whereas BP bits will only protect the upper half. In such a case, the value of the BP bits [1-1-0] will be used to control block protection during that operation cycle and only the upper half of the memory will remain protected. In the next power cycle, hardware reset, or software reset, the BP bits will be initialized using the BP_NV bits and will be updated to [1-1-1], protecting the entire memory array. To change the block protection configuration, BP bits can be programmed to some other value depending upon what fraction of memory is required to be unprotected. For the above example, the entire flash array shall remain protected upon every POR, hardware reset or software reset. To change this initialization configuration, BP_NV bits should be modified.