Author: RajathB_01 Version: **
Translation - Japanese: CCGxデザインでのVBUS FETスルーレート – KBA227425 - Community Translated (JA)
How can the turn-on slew rate of the VBUS FETs be controlled in CCGx designs? How can soft-start of VBUS FETs be implemented to limit inrush current in CCGx based designs?
VBUS FETs are used to connect the provider and consumer paths to the common Type-C VBUS path. Each path gets a set of FET switches, whose gates are driven by the CCGx controller. The VBUS_P_CTRL and VBUS_C_CTRL pins or signals control the provider and consumer path FETs, respectively. The gate signals for these two FETs are identical and can be dealt in same ways. Whenever a PMOS FET is used with a control signal which is Active high, an inverting NMOS gate driver is used to switch the main PMOS FETs. Table 1 shows the VBUS FET type and gate drive scheme used in different CCGx devices. CCG6 has integrated PMOS Gate driver blocks that allow programmable slew rate of P_CTRL FET to reduce inrush current.
Table 1. Gate Driving Scheme in Different CCGx Devices
VBUS FET Type
Gate Drive Type
Integrated NMOS gate driver
P_CTRL/C_CTRL varies from 0 to VBUS+2*VDDD
Integrated PMOS gate driver
Usually, large capacitance will be associated with the VBUS path due to filtering components or the load itself or power system output capacitance. The power paths have very low path resistance to minimize power dissipation. Therefore, an abrupt closing of the FET switch will change the path resistance from nearly infinite to just few milliohms, and the large capacitance will try to charge at a rapid rate. This causes a large VBUS current, referred to as Inrush Current. The magnitude of this inrush current can be high enough to trigger fault events, tripping the protection system on the SoC. If high enough, the current could damage the components along the path including the PCB traces. Arcing during connection could damage the connector pins.
To prevent this, you might like to implement a soft start-up feature, basically reducing the slew rate of the gate signal during turn-on of FET. This causes the FET channel resistance to decrease slowly, charging the VBUS capacitance at a lower rate, and hence reducing the inrush current on the power path.
To reduce the slew, you must decrease the slope of the gate signal. This can be achieved by an R-C circuit, essentially a filter with integrating nature, whose time constant can be adjusted based on the required smoothness. The resistor in this RC circuit can be an existing resistance on the gate driving path, specified in the reference schematics, or and additional resistance can be added without compromising the responsiveness of the gate of the FET.
Figure 1. Snubber Capacitors for Soft-start of PMOS FETs in CY4532 EVK
The resulting decrease in turn-on time will be affected by:
- FET gate capacitance (CGS/CGD)
- Capacitance of the RC circuit
- Overall resistance in the gate driver path
- Voltage at the drain of the FET (VDD)
You will have to consider these design factors and simulate the network to estimate the new turn-on time. Note that increasing the turn-on time excessively can cause significant power dissipation at the FET (switching loss) and the inability to switch power path within specification timings can result in false trigger of fault events.
Figure 1 and Figure 2 show the location of capacitors for soft-start as implemented in the EVKs. By default, these capacitors are not loaded (DNL) in Cypress EVKs, but you can load the appropriate value, if required.
Figure 2. Snubber Capacitors for Soft-start of NMOS FETs in CY4531 EVK