How to Support Two Dies for S70FS01GS - KBA228050

Author: yongq_16           Version: **

 

1. Differences between S25FS512S and S70FS01GS

The S25FS512S datasheet covers single-die operations, and the S70FS01GS datasheet covers the deltas from the single-die datasheet, as well as repeating much, if not all, of the content from the single-die datasheet. See the following sections that highlight the key differences.

 

2. Because the 1-Gbit part uses 1 Chip Select, does this part act like a single IC when it is in fact two silicon ICs?

To a certain degree, yes; but there are die effects.

Cypress designed the FS512S die so that there is a pad that can be connected inside the package to designate one die as the low address die, and the other as the high address die. Because the control and data signals are wired in parallel, command decoders in each die are active whenever Chip enable is active – so both dies listen to all command traffic. In this environment, a command can only be uniquely assigned to one die if the command has a 4-byte address argument to select the die address – high die for A26=1 or low die for A26=0. This means that certain classic SPI commands cannot be uniquely assigned to one die – these are carved out of the S70FS01GS datasheet (section 12.4).

It also means that Cypress introduced new commands with address arguments for key functions – these are listed in the highlighted sections of the S70FS01GS datasheet (section 12.4, plus the sections for each new command, special notes for legacy commands, and certain device characteristics).

Bulk Erase is an example of a classic “address-free” command that is not allowed in S70FS01GS. Cypress created a new command that takes an address argument so that Bulk Erase is active only on one die at a time. This command has an important restriction for the 2-die use case: Cypress qualified the 2-die package only for single-die operation. In other words, while the “address-free” Bulk Erase might be accepted by both dies, this use case is not allowed. That said, there are also some commands (without busy time) that work on both dies in parallel (section 12.4).

During reads, the auto-incrementing address rolls over at die boundaries. Thus, to read the full 2-die address space from one end to the other, two read commands are required.

Each die also has its own register set, so these must be correctly synchronized to comply with the datasheet.

So long as 4-byte address commands are used, programming and erasing have no die effects, because an address is always required for these commands. However, reading the status is die-dependent, so a die-address argument is required to retrieve the status from the correct die. Suspending and resuming program/erase operations also require new commands.

For reading the status on a single die, using the flash address 0x0 as the address argument doesn’t scale to a two-die part. It’s better to read the status at the same address argument used by the preceding program or erase command – this approach doesn’t require any special die-awareness in the status read function.

 

3. Does the user need to write to each Flash register?

Yes.

Probably the default register settings are fine. If not, they normally only need to be written once, at the production programming time, to establish your standard configuration. To do this in production or at runtime, the register access commands take a 4-byte address to select the die.  See the following sections in the datasheet:

  • 9.3.8 Read Any Register (RDAR 65h)
  • 9.3.9 Write Any Register (WRAR 71h)

There are also some register settings that are constrained by the presence of two dies in the package; these are highlighted in the highlighted sections of the datasheet in the following sections.

 

4. How is the 512-Mbit boundary controlled?  How do we determine which flash is being read or written?

Die-specific commands must have 4-byte address arguments, where A26=0 selects the low die, and A26=1 selects the high die.

The following datasheet excerpts are taken from the datasheet for S70FS01GS (002-03833 Rev *E):

Here’s a list of highlighted sections from the datasheet:

 

4.1       Page 2: Logic Block Diagram

4.2       Page 7: Section 1.2.2.9 – Other Legacy Commands Not Supported ad New Features

4.3       Page 7: Section 1.2.2.10 – New Features

4.4       Page 24: Table 4 – Thermal Resistance

4.5       Page 27: Section 4.6 – DC Characteristics

4.6       Page 28: Section 4.6.2 – Industrial Plus

4.7       Page 29: Section 4.6.3 – Extended

4.8       Page 31: Section 5.2.1 – Capacitance Characteristics

4.9       Page 40: Section 6.2.2 – Ball Grid Array 24-Ball FBGA

4.10        Page 41: Section 7.2 – Flash Memory Array

4.11        Page 62: Sectio 8.3 – Block Protection

4.12        Page 72: Section 9.1.2 – FS01GS DDP

4.13        Page 73 – Footnotes

4.14        Page 84: Section 9.3.8 – Read Any Register (RDAR 65h)

4.15        Page 86: Section 9.3.9 – Write Any Register (WRAR 71h)

4.16        Page 90: Section 9.4.3 – Dual I/O Read (DIOR BBh or 4DIOR BCh)

4.17        Page 91: Section 9.4.4 – Quad I/O Read (QIOR EBh or 4QIOR ECh)

4.18        Page 93: Section 9.4.5 – DDR Quad I/O Read (EDh, EEh)

4.19        Page 99: Section 9.6.3 – Bulk Erase (BE 60h or C7h)

4.20        Page 99: Section 9.6.4 – Bulk Erase Addressed (BEA FEh)

4.21        Page 101: Section 9.6.6 – Erase of Program Suspend (EPS 85h, 75h)

4.22        Page 103: Section 9.6.7 – Erase of Program Resume (EPR 7Ah, 8Ah)

4.23        Page 120: Table 56 – Device Geometry Definition for Bottom Boot Initial Delivery State

4.24        Page 125: Table 66 – CFI Alternate Vendor-Specific Extended Query Parameter

4.25        Page 134: Section 12.3 – Initial Delivery State

4.26        Page 135: Section 12.4 – FS01GS Behavior and Software Modifications

4.27        Page 136: Table 69 – FS01GS Parameter Sector Map Options

4.28        Page 137: Section  13 – Ordering Informatio

 

 

4.1   Page 2: Logic Block Diagram

 

4.2   Page 7: Section 1.2.2.9 – Other Legacy Commands Not Supported ad New Features

 

4.3   Page 7: Section 1.2.2.10 – New Features

 

4.4   Page 24: Table 4 – Thermal Resistance

4.5   Page 27: Section 4.6 – DC Characteristics

4.6   Page 28: Section 4.6.2 – Industrial Plus

4.7   Page 29: Section 4.6.3 – Extended

 

4.8    Page 31: Section 5.2.1 – Capacitance Characteristics

 

4.9    Page 40: Section 6.2.2 – Ball Grid Array 24-Ball FBGA

 

4.10   Page 41: Section 7.2 – Flash Memory Array

 

4.11   Page 62: Sectio 8.3 – Block Protection

 

4.12   Page 72: Section 9.1.2 – FS01GS DDP

 

4.13   Page 73 – Footnotes

 

4.14   Page 84: Section 9.3.8 – Read Any Register (RDAR 65h)

 

4.15   Page 86: Section 9.3.9 – Write Any Register (WRAR 71h)

 

4.16   Page 90: Section 9.4.3 – Dual I/O Read (DIOR BBh or 4DIOR BCh)

 

4.17   Page 91: Section 9.4.4 – Quad I/O Read (QIOR EBh or 4QIOR ECh)

 

4.18   Page 93: Section 9.4.5 – DDR Quad I/O Read (EDh, EEh)

 

4.19   Page 99: Section 9.6.3 – Bulk Erase (BE 60h or C7h)

 

4.20   Page 99: Section 9.6.4 – Bulk Erase Addressed (BEA FEh)

 

4.21   Page 101: Section 9.6.6 – Erase of Program Suspend (EPS 85h, 75h)

 

4.22   Page 103: Section 9.6.7 – Erase of Program Resume (EPR 7Ah, 8Ah)

 

4.23 Page 120: Table 56 – Device Geometry Definition for Bottom Boot Initial Delivery State

 

4.24   Page 125: Table 66 – CFI Alternate Vendor-Specific Extended Query Parameter

 

4.25   Page 134: Section 12.3 – Initial Delivery State

 

4.26   Page 135: Section 12.4 – FS01GS Behavior and Software Modifications

 

4.27   Page 136: Table 69 – FS01GS Parameter Sector Map Options

 

4.28   Page 137: Section 13 – Ordering Information