Missing 1st Transmit Data Bit in FM3 CSIO Normal Synchronous Transfer Mode/Slave – KBA227551

Version 4

    Author: TakashiM_61         Version: **


    Translation - Japanese: FM3 CSIOの通常の同期転送モード/スレーブで最初の送信データビットが欠落している – KBA227551 - Community Translated (JA)


    FM3 Clock Synchronous Serial Interface (CSIO) is the general-purpose serial data communication interface (supporting the SPI) to allow synchronous communication with an external device. CSIO is configurable for some transfer operations, for example Normal transfer (I), Normal transfer (II), SPI transfer (I), and SPI transfer (II). CSIO can be configured as Master or Slave.

    See the 32-Bit Microcontroller FM3 Peripheral Manual Communication Macro Part.


    On the following CSIO transfer operation,

    • Normal synchronous transfer mode (SCR.SPI=0)
    • Slave mode (SCR.MS=1)
    • Serial clock disabled: the serial clock “SCK” is input from Master to Slave.


    If data transmission is enabled (SCR:TXE=1) and if the first transmit data is written in the Transmit Data Register (TDR) at a time other than the serial clock (SCK) signal mark level, the first data bit is not output and the data transmission may fail.


    After the data transmission is enabled (SCR:TXE=1), the first transmission data must be written in the TDR at the signal mark level of the serial clock (SCK). With the following example (the falling edge of SCK), the transmission data must be written in the TDR before 2 internal bus clock (APB2 bus clock : PCLK2). Otherwise, the first transmission data is not output on TX line.