# CRC Implementation in CY15x104QSx F-RAM™ – KBA220252

Version 2

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Question:

How is CRC implemented in CY15x104QSx F-RAM?

Cypress CY15x104QSx FRAM supports two types of CRC operations:

1. Data CRC: CRC calculation on user-defined memory block.
2. Bus CRC: CRC calculation on SPI bus transactions in real time

Data CRC: CRC calculation on user-defined memory block

The CY15x104QSx F-RAM device can calculate CRC on a user-defined memory block in the chip. You can specify the starting address and ending address of the memory block on which CRC calculation should be performed using the “CRC Calculation (CRCC, 5Bh)” instruction. The calculated CRC value will be stored in CRC Register (CRCR). The Read Any Register (RDAR, 65h) command can be used to read the calculated CRC value from CRCR. The CRC algorithm uses a 32-bit polynomial (CRC-32C), which receives the data ordered as {data[7:0], data[15:8], data[23:16], data[31:24]} assigned to CRC[31:0]. The 32-bit polynomial (0x1EDC6F41) is represented as follows:

X^32 + (X^28+X^27+X^26+X^25+X^23+X^22+X^20+X^19+X^18+X^14+X^13+X^11+X^10+X^9+X^8+X^6+1)

The following points should be taken into account while calculating CRC on a user-defined memory block:

• The Ending Address (EA) should be at least one 32-bit aligned word (the two least significant address bits A[1:0] should be set to ‘00’) higher than the Starting Address (SA). If EA < SA + 4, CRC calculation will be aborted and the device will return to Standby mode. When EA < SA + 4, the CRC Register will hold indeterminate data.
• CRC register (CRCR) bits are initialized with all 1s every time CRC calculation is initiated. A POR, any reset, or exit DPD mode will also reset the CRC register value to all 1s.

While CRC calculation is in progress, the WIP (Work In Progress) bit in Status Register 1 (SR1[0]) will be set to '1'. When CRC calculation operation is complete, the WIP bit will be set to '0'. So, this bit can be used to check the completion status of the CRC operation.

The CY15x104QSx device supports the CRC suspend operation. The CRC suspend (EPCS, 75h) instruction can be used to suspend an ongoing CRC operation which allows memory read commands to access the memory. The CRC Resume (EPCR, 7Ah) command resumes the CRC operation suspended with the EPCS command.

Bus CRC: CRC calculation on SPI bus transactions in real-time

The CY15x104QSx device calculates CRC on every SPI transaction, including command entry, address entry, mode bits, data-in, and data-out using the CRC-32C polynomial. The Bus CRC is not calculated on dummy bytes where the data bus becomes don’t care and is not driven by either CY15x104QSx or the host during any operation. The CRC-32C polynomial (0x1EDC6F41) is represented as follows:

X^32 + (X^28+X^27+X^26+X^25+X^23+X^22+X^20+X^19+X^18+X^14+X^13+X^11+X^10+X^9+X^8+X^6+1)

The calculated bus CRC value is stored in the Bus CRC (BCRC) register and is read using the Read BUS CRC Register (RBCRC, 64h) command. The BCRC register is cleared to 0xFFFFFFFF as soon as the RBCRC transaction is complete. The BCRC_DIS bit in Mode Register (MR[7]) enables or disables the bus CRC feature in CY15x104QSx. If the BCRC_DIS bit is set to ‘1’, bus CRC is disabled; when the BCRC_DIS bit is set to ‘0’, the bus CRC is enabled. When bus CRC is disabled, reading the BCRC register returns an indeterminate value. When bus CRC is enabled, the RBCRC command should be issued to reset CRC calculation back to the default before continuing.

When CY15x104QSx is active with its chip select (CS#) asserted LOW and bus CRC is enabled, it captures every transaction (input and/or output) on the SPI bus for CRC calculation. Depending upon the SPI mode enabled during the access - single SPI, dual SPI (SPI), or quad SPI (QPI), the sampled 1/2/4 data bits in each clock cycle are clocked into the CRC Generator, which calculates the CRC checksum and stores the result in the BCRC register. If an SPI operation is aborted in between by deasserting the CS# signal, the data transferred until then will be clocked into the CRC Generator for CRC calculation.

The bus CRC value resets to 0xFFFFFFFFh with the following conditions:

1. Power on reset (POR)
2. Hardware reset
3. Software reset
4. RBCRC command
5. Exit from Deep power down mode
6. Exit from Hibernate mode

Both these CRC features of CY15x104QSx ensure high levels of data integrity in applications.