Version: *A
Translation - Japanese: CY15x104QSx F-RAM™のECC – KBA220250 - Community Translated (JA)
Question:
How does ECC work in Cypress CY15x102QSx/CY15x104QSx F-RAM?
Answer:
Cypress CY15x102QSx/ CY15x104QSx F-RAM has on-die ECC, which supports 1-bit error detection and correction, and 2-bit error detection (no automatic error correction in this case).
CY15x102Qx/ CY15x104Qx internally calculates ECC on every 8 bytes (64 bits) of data unit. If a 2-bit error is detected during read operation, the 2DB (2-Bit ECC Detection) bit in the ECC status register will be set to '1'. You can read the ECC status register after a read operation to check if any 2-bit error detection has happened. The 2DB bit can be cleared to ‘0’ using the Clear ECC Status Register (CLECC, 1BH) command.
The Address Trap Register (ADDTRAP) and the ECC Detect Count (ECCDC) are the other two associated registers that provide ECC information. The ADDTRAP register captures and retains the data unit address of the first data unit with 2-bit error. The subsequent unit addresses with 2-bit error will not be captured in the ADDTRAP register.
The ECCDC register holds the total 2-bit error detection count which increments by ‘1’ every time a 2-bit error is detected. ADDTRAP and ECCDC are volatile registers, which are cleared to '0' after every power on reset (POR), hardware and software reset, and exit from low-power modes (Hibernate and DPD). The status of ADDTRAP and ECCDC registers are retained during Active and Standby modes.
The ECC status register can be read using the ECCRD (19H) command. You should use the following command sequence to read the ECC status register.
- Issue the ECCRD command.
- Send the 3-byte ECC data unit address (data unit for CY15x102QSx/ CY15x104QSx is 8 bytes; A0, A1, A2, are internally ignored).
- Send the dummy cycles as configured (it uses the latency cycle configured for memory read).
- Read the 8-bit ECC status register.
Other ECC registers (ADDTRAP and ECCDC) can be read using the RDAR (65H) command.
