Author: VasanthR_91 Version: **
Translation - Japanese: SAR ADCのVrefを動的に変更する – KBA227544 - Community Translated (JA)
You can select the Vref voltage in the Component configuration window from internal 1.024V, VDDA/2, or VDDA (see Figure 1).
Select the “Bypass” option to route the Vref to a GPIO pin, which can then be used to connect a bypass capacitor. Consult the device family datasheet pinout section [BJ1] [VRS2] to know the exact GPIO pin which is used as Vref bypass (Datasheets: PSoC 3, PSoC 5LP, PSoC 4, and PSoC 4 BLE).
Figure 1 : Vref select in component editor
The CYREG_SAR_CTRL register has the selection options for Vref, which can be modified at runtime. Set bit 7 of the CYREG_SAR_CTRL register to ‘1’ to enable the bypass capacitor option. Use Bit 6:4 to select the specific Vref setting.
Pseudo code:
uint32 temp;
temp = CY_GET_REG32(CYREG_SAR_CTRL);
temp &= 0xFFFFFF0F;
temp |= 0x000000C0; //1.024 reference
CY_SET_REG32(CYREG_SAR_CTRL, temp);
CyDelay(100); // Wait for 100ms for ADC to settle to the new Vref
temp = CY_GET_REG32(CYREG_SAR_CTRL);
temp &= 0xFFFFFF0F;
temp |= 0x000000E0;
CY_SET_REG32(CYREG_SAR_CTRL, temp); //VDDA/2 reference
CyDelay(100);
temp = CY_GET_REG32(CYREG_SAR_CTRL);
temp &= 0xFFFFFF0F;
temp |= 0x000000F0; // VDDA reference
CY_SET_REG32(CYREG_SAR_CTRL, temp);
CyDelay(100);
The ADC takes some time to settle to the new Vref setting. A delay of 100 ms is recommended for the ADC to stabilize to the new Vref setting and give the correct output.