PFM Switching Behavior of the DD5V Channel in S6BP50x PMIC – KBA227373

Version 4

    Author: SadaharuK_26          Version: **


    Translation - Japanese: S6BP50x PMIC の DD5V チャネルの PFM スイッチング動作について - KBA227373 - Community Translated (JA)


    The simplified equivalent block diagram of DD5V channel in S6BP50x PMIC is shown in Fig. 1.

    When you set the PWM/PFM switching operation to automatic (SYNC=L), the PMIC switches between PWM (2-MHz switching operation) and PFM with the Control Logic depending on the PFMCOMP output. At a light load current, the output level of ErrAMP becomes lower and the PMIC shifts to PFM operation.


    The switching operation of the PFM in a light load, which is mainly decided by CLKCOMP and IRCOMP, has a fixed Low-side FET ON time of about 600 ns and a fixed High-side FET ON time of about 600 ns. The Low-side FET turns ON when IRCOMP and CLKCMP both become HIGH with the confirmation of the High-side FET’s OFF state. When VOUT5V rises at a light load, the output of CLKCOMP keeps LOW; therefore, the switching operation will be terminated during that period. The switching waveform of the PFM is shown in Fig. 2.


    Fig.1 Equivalent block diagram of DD5V channel in S6BP50x PMIC

    Fig. 2 PFM switching waveform of DD5V channel in S6BP50x PMIC