On the F2MC-16LX Family MCUs, how a USB Bus reset condition is detected is determined by the relationship between the USB operation clock stop mode specified by the USTP bit in the UDCC register, and the USB suspend detection mode specified by the SUSP bit in the UDCS register.
For more details of USB operation clock stop mode and suspend detection mode, see Chapter 13, “USB Function” in the F2MC-16LX MB90330A Series Hardware Manual.
Figure 1. USTP Bit in UDCC Register
Figure 2. SUSP Bit in UDCS Register
The following table summarizes the cases where a USB Bus reset can be detected by USB modes.
USB Bus Reset
Can be detected
Can be detected
Can NOT be detected
Can be detected
In this case, the assumption is that the application does not use USB and has entered a low-power mode by turning off the USB (USB OFF).
See the note on “[bit4] USTP:USB operation clock stop bit” in F2MC-16LX MB90330A Series Hardware Manual to learn how to transition to Pattern 3 and how to return to Pattern 1.
Note on “[bit4] USTP:USB operation clock stop bit”
If the USTP bit is not used in the stop mode, wait for 3 cycles or 43 cycles to elapse in FULL speed or in LOW speed (that is supported only in HOST mode) so that you can ensure that the reset operation will function when you have set RST=1. You may clear the USTP bit and the RST bit at once.
The USB macro is reset by UDCC.RST=1. The clock for USB can be gated by UDCC.USTP=1. This means that the USB macro enters Stop mode (pure low power consumption mode) by setting UDCC.RST=1 and UDCC.USTP=1, and that the CPU is always running.
In this case, the assumption is that the application uses USB and the lowest power consumption is expected in USB Suspend mode. While in the Pattern 4, the USB bus of the USB macro transitions to a special state to monitor the USB bus status (Bus reset, Wakeup). This means that the USB macro enters Stop mode and keeps monitoring the USB bus status.
See the note on “UDC Control Register (UDCC)” in F2MC-16LX MB90330A Series Hardware Manual to learn how to transition to Pattern 4 and return to Pattern 1.
Note on “UDC Control Register (UDCC)”
The UDC control register (UDCC) should be set when bit7:RST=1 and not be rewritten when USB is in operating. However, bit 6 of RESUM and bit 4 of USTP are exclusive. RESUM of bit6 should be set or reset in suspend status of USB only by the remote wake-up enable status due to the following commands. Set USTP of bit4 to "1" before entering the stop mode state. To deselect the stop mode, set the order of SUSP in the UDCS and USTP in the UDCC to "0".
To return to Pattern 1, UDCS.WKUP is set to “1” if the USB bus status has changed due to a Bus reset or Wakeup.
- If there is a bus wakeup, the wakeup flag “UDCS.WKUP” is set. This generates an interrupt.
- If a Bus reset occurs, the wakeup flag “UDCS.WKUP” is set, and an interrupt is generated. Then, the UDCS.SUSP and UDCC.USTP bits are cleared, and the USB clock is started. The USB macro sets the bus reset flag after the Bus reset time expires.