Author: AtsushiT_61 Version: **
Translation - Japanese: タイトル：サイプレス車載PMICの電流モードアーキテクチャ – KBA225717- Community Translated (JA)
As shown in Figure. 1, current mode control uses an inductor current feedback loop in addition to the voltage feedback loop.
- Clock signal of the IC internal oscillator sets RS-FF and turns ON the High-side FET.
- Inductor current increases as High-side FET turns ON. This current is converted into the voltage signal Vs.
- Comparator ICOMP compares Vs and VC, which is the output voltage of the error amplifier.
- When Vs becomes equal to VC, the RS flip flop (RS-FF) resets and the High-side FET turns OFF.
- A clock signal (CLK) of fixed frequency sets RS-FF again and initiates the next switching cycle.
Consequently, the FB voltage is controlled to be equal to the reference voltage VR and output voltage is stabilized.
Fig.1 Current Mode Control block diagram and switching waveform
Main advantages of current mode control are good line regulation, simple phase compensation circuitry, robustness under large load fluctuation, and a cycle-by-cycle current limit.
Line regulation is the change of output voltage due to the input voltage change and is affected by the gain of the output control transfer function. In current mode architecture, the gain of the output control transfer function is independent of VIN, which results in good line regulation performance.
Unlike voltage mode architecture, which has a second-order pole in the output control transfer function, current mode architecture has a single pole at low frequency due to the additional current control loop. Therefore, the phase compensation circuitry simplified thus can be easily integrated into the PMIC. Therefore, the BOM cost is lower and the PMIC quiescent current can be greatly reduced.
Additionally, current mode architecture directly monitors and controls the inductor current. With the current limit, the PMIC using current mode contributes to a safer power system.