Author: ShanmathiN_06 Version: **
Translation - Japanese: PSoC 6 MCUデバイスのファームウェアを介したSPI I/Oピンの制御 - KBA226844 - Community Translated (JA)
How can the SPI pins (CLK, MOSI, MISO, SS) for PSoC® 6 MCU devices be controlled during runtime in the firmware?
After placing the SCB_SPI component in TopDesign, you can disable/enable the SPI Master/Slave functionality on the fly. The[HM1] solution provides the steps to control pins in firmware and the code snippet implements the suggested solution using APIs.
Solution in firmware:
In general, pins can be controlled by either firmware or hardware. By default, all the SPI I/O pins are controlled by the SCB hardware block; so, it is necessary to disconnect the SPI pins from the SCB block to enable control in firmware.
Follow these steps to disconnect the hardware connection between SPI I/O pin and SPI SCB and enable control in firmware:
- Write 'bit 0' to the bits of HSIOM_PRTx_PORT_SELx register corresponding to SPI I/O pin.
- Set the drive mode of the SPI I/O pin by modifying the GPIO_PRTx_CFG register.
For more details, see the I/O System (HSIOM) in the Architecture Technical Reference Manual and Register Technical Reference Manual. [HM2] You can use the following code snippet to implement the suggested solution using APIs [Consider SPI CLK pin to be P10.2, which is to be controlled in firmware].
// Variable to store the default SCB_SPI configuration settings
// Variable to store the new drive mode settings required by the application
// If the drive mode to be set is high impedance, then drive_mode = 0xFFFFF0FF
// Save the HSIOM configuration for SCB_SPI
temp = CY_GET_REG32(CYREG_HSIOM_PRT10_PORT_SEL0);
// Configure SPI CLK pin to be controlled in firmware
CY_SET_REG32 (CYREG_HSIOM_PRT10_PORT_SEL0, temp & 0xFFE0FFFF);
// Set the drive mode of SPI CLK pin
CY_SET_REG32 (GPIO_PRT10_CFG, drive_mode);
// Load the default SPI functionality (i.e) CLK pin is connected to SCB_SPI hardware block
CY_SET_REG32 (CYREG_HSIOM_PRT10_PORT_SEL0, temp);
All SCB blocks and other peripherals such as TCPWM, could also be controlled in firmware by modifying the HSIOM and drive mode registers.