MCU Reset under SPI Enhanced High Performance Feature Enabled - KBA226826

Version 3

    Author: JaeH_21           Version: **


    Translation - Japanese: SPI拡張高性能機能が有効な状況でのMCUリセット - KBA226826 - Community Translated (JA)



    Why does accessing SPI flash memory fail after resetting the MCU under SPI continuous read mode (Enhanced High Performance (EHP) feature enabled)?



    If the MCU is reset without resetting SPI flash memory under continuous EHP read mode, the successive SPI instruction will be recognized as a MSB

    in address phase, and not as a SPI instruction in instruction phase. As a result, the operation issued by the MCU will not work as expected. This happens due to the following reason.

    Dual I/O Read or Quad I/O Read in SDR or DDR mode provides a method to improve read throughput by removing the instruction sequence. Enabling the feature can be done by controlling the mode bits of the current read operation to determine whether the next read operation has one-byte instruction code.  Figure 1 shows an example of Quad I/O Read operation without read instruction phase, but starting with address phase.

    Figure 1.Quad I/O Read Operation

    EHP read mode will be released at the following cases:

    • The read operation sets the mode bits at any value other than Axh. At the next time CS# raising high, the device will be released from EHP Read mode
    • Mode Bit Reset command (MBR FFh). This command returns the device from continuous EHP Read mode back to normal standby awaiting any new command
    • Hardware RESET# or Power-On-Reset


    Note: It is recommended to add a Mode Bit Reset command to the application startup code or perform a hardware reset to the device with the MCU reset.


    Figure 2. Recovering read mode from EHP read mode