Author: VincentH_06 Version: **
Translation - Japanese: サイプレスデュアルダイスタックQSPI NORフラッシュの典型的なアプリケーション - KBA226829 - Community Translated (JA)
Cypress has S79FL-S, S70FL-S, and S70FS-S series for dual-die stack QSPI NOR flash. What are the differences and typical application of these series?
S79FL-S, S70FL-S, and S70FS-S series are Cypress dual-die stack QSPI NOR flash. These three series can provide up to 1 Gbit density, but the pin assignment and internal connections are different:
- S79FL01GS: Has two suites of QSPI control and signal pins, and can be considered as two separate S25FL512S dies packed in the single chip.
Figure 1. S79FL01GS Block Diagram
For a host with two SPI controllers, which can also support dual-quad SPI mode, one S79FL01GS can be used instead of two standalone S25FL512S chips onboard. This reduces the PCB size and simplifies the board design.
Figure 2. S79FL01GS Application on Host with Dual-quad SPI Controllers
If the host only has one SPI controller with eight I/O ports, the CS# and SCK# pins on dual-die can be multiplexed to combine the two-way QSPI signals to improve the bandwidth.
Figure 3. S79FL01GS Application on Host with Single Eight I/O SPI Controller
- S70FL01GS: Has two dedicated CS# pins with shared SCK and I/O pins; die can be differentiated by selecting CS#1 or CS#2.
Figure 4. S70FL01GS Block Diagram
For a host with two SPI controllers, which does not support dual-quad SPI mode, one S70FL01GS can be used instead of two standalone S25FL512S chips onboard. I/O and SCK can be multiplexed to reduce pin count onboard and the PCB size. Note that the operations on two SPI controllers should be atomic; only one master can access the flash at a time.
Figure 5. S70FL01GS application on Host with Two Standalone Quad SPI Controllers
- S70FS01GS: Two dies share CS#, SCK, and I/O pins; die can be differentiated by address scope (0x0000_0000-0x03FF_FFFF for lower 512Mbit die, 0x0400_0000-0x07FF_FFFF for upper 512 Mbit die).
Figure 6. S70FS01GS Block Diagram
If the host only has one SPI controller, S70FS01GS can be used to archive 1 Gbit memory area without extra control or signal pins. Make sure you always keep the same register configurations on both dies of S70FS01GS, and replace commands without address with commands with address input. For more information, see section 12.4 of S70FS01GS.
Figure 7. S70FS01GS Application on Host with One Quad SPI Controller
Picture 1. S70FS01GS application on host with only one quad SPI controller
A host with two standalone quad SPI controllers can also use two S70FS01GS chips to achieve 2 Gbit QSPI NOR flash density for large memory space requirement.
Figure 8. S70FS01GS Application on Host with Two Standalone Quad SPI Controllers to Achieve 2 Gbit Density
· S79FL01GS: Has two suites of QSPI control and signal pins, and can be considered as two separate S25FL512S dies packed in the single chip.