SPI clock frequency for Cypress SPI NOR flash device – KBA226830

Version 2

    Author: SudheeshK_26           Version: **

     

    Question:

    Is it necessary to keep the SPI clock frequency for Cypress SPI NOR flash devices always constant? Is it possible to change clock frequency within an SPI operation (CS# cycle)?

     

    Answer:

    It is not necessary to keep the SPI clock frequency constant always for Cypress SPI NOR flash devices. User can perform different SPI operations at different frequencies, if they are within the operating frequency range. But, it is not recommended to change SPI clock frequency within an SPI operation (CS# cycle).Changing SPI clock frequency within an SPI operation will violate the below datasheet specs (from S25FL512S datasheet).

     

    tWH, tCH

    Clock High Time 

    45% PSCK

    ns

    tWL, tCL

    Clock Low Time 

    45% PSCK

    ns

     

    However, it is possible to have breaks in SCK signal between sending each byte.

    For example:

    1. It is possible to make SCK signal LOW for a longer duration in between sending command and address during a program operation.
    2. It is possible to make SCK signal LOW for a longer time after sending RDSR command and before reading the SR value back.

    Below waveform diagrams illustrate these two scenarios.

    Figure1: Single byte program operation (Includes WREN command at the first CS# cycle in below diagram)

    Figure 2: Single byte read operation

    SPI clock frequency should be constant for each byte transaction (command or address or data) during a SPI operation (8 clock cycles).