Author: AtsushiT_61 Version: **
Translation - Japanese: S6BP401AデータシートのTPPG条件 - KBA226545 - Community Translated (JA)
Table1 shows electrical characteristics example of the power good monitor function of S6BP401A, and Fig.1 shows the timing chart of the S6BP401A power good monitor output.
Table1. Electrical Characteristics of Power Good Monitor function for of S6BP401A
Fig.1 Power Good Monitor Output Timing Chart
TPPG is the delay for the PG pin to become LOW after VOUTx rising to the OVP threshold (VPGOV) or falling to the UVP threshold (PGUVPLH). The delay varies depending on the differential level between VOUTx and the OVP / UVP threshold. The higher the differential level, the smaller the delay. The value in the datasheet is defined as a value when there is a difference of 5% from the detection reference value. In case of over voltage threshold (VPGOV) = 106% typ, the TPPG: 4 µs typ is defined at the condition of VOUTx rising to + 11% (= 6 + 5 %) from the setting value.