Author: AlbertB_56 Version: **
Translation - Japanese: S25FLxxxSシリーズ フラッシュでのモード ビットの定義と実装 - KBA226707 - Community Translated (JA)
What are Mode Bits and how are they implemented with the S25FLxxxS series Flash?
The Mode Bits eliminate the overhead of SIO instructions when repeating the same type of READ command. The Mode Bits follow the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. The next command does not provide an instruction byte, but only a new address and Mode Bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands. Mode Bits might be followed by a read latency period before READ data is returned to the host. See the S25FL512S or S25FL128S/FL256S datasheet for more details.
The High-Performance settings provide latency options that are the same or faster than alternate source SPI memories. These settings provide Mode Bits only for the Quad I/O Read command. The Enhanced High-Performance settings similarly provide latency options that are the same or faster than additional alternate source SPI memories and adds Mode Bits for the DDR Quad I/O, DDR Dual I/O, DDR Fast, Quad I/O, and Dual I/O READ commands. See the S25FL512S or S25FL128S/FL256S datasheet for more details.
Implementation: In Enhanced High-Performance settings, the Mode Bits control the length of the appropriate READ (DDR Quad I/O, DDR Dual I/O, DDR Fast, Quad I/O, Dual I/O) Operation. If the upper nibble (I/O[7:4]) and lower nibble (I/O[3:0]) of the ‘Mode Bits’ are complementary (i.e. 5h and Ah), the device transitions to the appropriate continuous READ Operation and the next address can be entered (after CS# is raised high and then asserted low) without requiring the appropriate READ command. See the S25FL512S or S25FL128S/FL256S datasheet for more details.
The Mode Bit Reset (MBR FFh) command can be used to return the device from continuous High-Performance and Enhanced High- Performance read modes to the normal standby mode, awaiting any new command. Some device packages lack a hardware RESET# input and a device that is in a continuous high-performance read mode may not recognize any normal SPI command, so the device might not recognize a system hardware reset or software reset command It is recommended to use the MBR command after a system reset when the RESET# signal is not available, or before sending a software reset to ensure the device is released from continuous high performance read mode. The MBR command sends Ones on SI or I/O0 for eight SCK cycles. I/O1 to I/O3 are ‘don’t care’ during these cycles. See the S25FL512S or S25FL128S/FL256S datasheet for more details. Note: Each READ command ends when CS# returns Logic-High at any point during data return. During the appropriate continuous READ command selected, if the Mode bits are not complementary, then the next time CS# is raised to Logic-High and then asserted to Logic-Low the device will be released from the appropriate continuous READ operation. CS# must not return to Logic-High during the Mode Bits or dummy cycles before data returns to the host, as this may cause the Mode Bits to be captured incorrectly; making it indeterminate as to whether the device remains in the Enhanced High-Performance read mode. See the S25FL512S or S25FL128S/FL256S datasheet for more details.
Figure 1. Continuous DDR Quad I/O Read Subsequent Access (3-Byte Address, HPLC=11b)
Figure 2. DDR Quad I/O Read Initial Access (4-Byte Address, EEh or Edh [ExtAdd=1], EHPLC=01b)
Figure 3. Continuous DDR Quad I/O Read Subsequent Access (4-Byte Address, EHPLC=01b)
Figure 4. Mode Bit (MBR FFh) Reset Command Sequence