Software Application Notice for S70FS01GS NOR Flash - KBA225966

Author: vincenth_06         Version: **

 

Question:

S70FS01GS contains dual S25FS512S dies but has only a single Chip Select (CS#) pin. How can I access and configure flash? Is there any restriction or special notice on S70FS01GS?

 

Answer:

S70FS01GS provides a single Chip Select (CS#) with dual S25FS512S dies stacked within the same package to provide 1 Gbit of memory. To make sure the entire address range can be accessed and both the 512 Mbit devices have the same behavior, consider the following guidelines and configuration:

  • Flash Address and Access

The total address space on S70FS01GS is over the 3-byte address limit, so you need to use the 4-byte address command to fully access the 1 Gbit space and the registers on the two 512 Mbit devices. The 4BAM (B7h) command is used to enter the 4-byte address mode.

With 4-byte address command, one half responds to commands directed to the lower 512 Mbit (0x0000_0000 to 0x3FFF_FFFF) of the address space and the other half responds to commands directed to the upper 512 Mbit (0x0400_0000 to 0x7FFF_FFFF) of the address space.

The sequential read output will not cross the 512-Mbit boundary and wrap around to the lowest address of the same half. For example, a sequential read at address 0x03FF_FFFF on S70FS01GS will be followed by a read wrapped at 0x0000_0000. A sequential read at address 0x7FFF_FFFF of an S70FS01GS will be followed by a read wrapped at 0x0400_0000.

  • Commands

Due to the single CS# pin on S70FS01GS, some legacy register access commands which do not have an explicit address in the command are not supported on S70FS01GS. For example, commands WRR (01h), RDCR (35h), RDSR1 (05h), RDSR2 (07h) are not supported on S70FS01GS to access corresponding registers. Use the command RDAR (65h) and WRAR (71h) followed with 4-byte register address.

There are still commands on S70FS01GS which will take effect on both 512 Mbit dies in parallel with no need for a specific address. For example, commands 4BAM (B7h), CLSR (82h or 30h), RST (99h), WREN (06h), and WRDI (04h) still operate on both 512 Mbit devices for the software compatibility and convenience perspective.

  • Registers and Configurations

The registers on both 512Mbit devices should be configured separately, command RDAR (65h) and WRAR (71h) are used to access and configure registers, the followed register addresses are described in Table 9.2 in the datasheet. The base address starting with 0x0000_0000 is for the lower half 512Mbit die, the base address starting with 0x0400_0000 is for the upper half 512Mbit die.

For both the 512 Mbit devices to have the same behavior, most of the register configurations should be the same, especially for the following register bits:

    • SR1NV[7] and SR1V[7] - Write Enable Latch bits: These bits should be the same to make sure the write or erase operations can be applied on the entire 1-Gbit space.
    • CR1NV[1:0] and CR1V[1:0] CR2NV[6] and CR2V[6] - QUAD and QPI mode bits: These bits should be the same for both the 512 Mbit devices to work in the same mode.
    • CR2NV[7] and CR2V[7] - 3 or 4 byte address mode bits: These bits should be the same to support the same address length.
    • CR2NV[5] and CR2V[5] - IO3 or RESET# multiplex bits: These bits should be the same to make both devices recognize the signal on IO3/RESET# pin correctly.
    • CR2NV[3:0] and CR2V[3:0] - Dummy cycle bits: These bits should be the same to keep the correct reading latency.
    • CR3NV[5:4] and CR3V[5:4], CR3NV[1:0] and CR3V[1:0] - Blank check, page buffer wrap, erase sector, and legacy reset bits: These bits should be the same to keep the same configuration on both the 512 Mbit devices.
    • CR4NV[7:4] and CR4V[7:4], CR4NV[1:0] and CR4V[1:0] – Impedance, wrap enable, and length bits: These bits should be the same to keep the same configuration on both the 512 Mbit devices.

 

  • 4KB Parameter Sector and Block Protection Usages

Although most of the register configurations should be the same on both the 512 Mbit devices, some configurations should be different to make it a monolithic 1 Gbit device.

    • CR1NV[2] and CR1V[2], CR3NV[3] and CR3V[3] - 4 KB parameter sector configuration bits: The 4KB parameter sectors may optionally be located only at the bottom or top of the 1 Gbit address space. This means only three combinations of these two configuration bits are supported:

 

Device

Lower FS512S

Upper FS512S

Parameter Sectors Location

CR1NV[2]( TBPARM_O)

CR3NV[3]( 20h_NV)

CR1NV[2]( TBPARM_O)

CR3NV[3]( 20h_NV)

None (Uniform Sectors)

X

1

X

1

Bottom

0

0

X

1

Top

X

1

1

0

Default Configuration

0

0

0

0

    • If you want to use S70FS01GS with Linux, note that the current Linux MTD driver only supports uniform sector size. For more information, see S25FS-S Support Under Linux - KBA218975.
    • SR1NV[4:2] and SR1V[4:2] - Block protection bits: Block protection must be configured in each FS512S, as desired, to protect the sectors in each 512 Mbit device. Note that because the configuration of TBPROT_O bits in each device must be c the same, BP protection range is oriented top or bottom in both devices.

For the detailed and full features supported on S70FS01GS, see section 12.4 of the device datasheet.