ECC Injection Tests in Traveo MCUs - KBA225469

Version 4

    Author: maheshb_81    NambirajanN_11        Version: **

     

    Translation - Japanese: Traveo MCUのECCインジェクションテスト - KBA225469 - Community Translated (JA)

     

    This guide explains Error Correction Code (ECC) Injection Tests in Traveo MCUs.

     

    In Traveo MCUs, there is built-in ECC logic that helps in detecting and correcting single-bit errors or in detecting 2 bit errors. This built-in ECC logic is available within many peripheral memories of Traveo MCUs such as TCRAM, TCFLASH, VRAM, Work Flash, IRC Vector Address RAM, CAN FD RAM, and SYSRAM.

     

    Traveo MCUs also provide necessary hardware and Test Registers (known as Injection Registers) that could simulate the data corruptions and check if the ECC logic is able to detect or correct these errors. These tests can be performed as part of the functional safety module associated with the product design.

     

    This guide focuses on the details of these Injection Registers and how they can be used to simulate the errors. The guide also provides sample code fragments that can be used to test the ECC feature available within a peripheral memory.