Author: ShanmathiN_06 Version: **
How can IDAC calibration percentage, sense clock source, sense clock frequency, and modulator clock frequency for CapSense® designs be set with gradual environmental variations?
When the CapSense sensors are subjected to gradual environmental variations, the baseline may track the raw counts gradually due to changes in temperature, humidity, or other environmental conditions.
Typically, auto calibration will calibrate the IDAC such that raw counts are calibrated to 85%, 70%, and 40% of the maximum raw counts for CSD single IDAC, CSD dual IDAC, and CSX respectively.
However, gradual environmental variations could result in the following undesirable scenarios:
- Raw counts increase gradually and may get saturated to maximum raw counts.
For example, in CSD-based designs, baseline (85% or 70% of maximum raw counts) will gradually follow the raw counts and may reach even 95% of maximum raw counts and eventually get saturated. Similarly, in CSX-based designs, baseline (40% of maximum raw counts) will gradually follow the raw counts and may reach even 5% of maximum raw counts and eventually get saturated. To avoid the raw counts from increasing gradually and saturating to maximum raw counts, do not calibrate the raw counts to the typical calibration percentage. Instead, calibrate the raw counts to a specific percentage depending on the type of CapSense sensors to allow room for changes in baseline due to gradual temperature and humidity variations.
To change the calibration percentage, disable IDAC auto-calibration and set IDAC codes manually or enable IDAC auto-calibration and use the CapSense_CSDCalibrateWidget () API to set the raw count calibration to a lesser and higher percentage for CSD and CSX-based CapSense designs, respectively.
- Raw counts decrease gradually and may hit flat spot regions. Flat spots are more prominent at 25%, 50%, and 75% of the maximum raw counts. In addition, there is a huge probability of raw counts hitting a flat spot region when calibration percentage is changed.
Follow these steps to reduce the width of flat spots:
- Set the sense clock source to PRS or SSC and not to direct clock, as this will reduce the width and number of flat spots and hence, will increase signal in flat spot regions.
- For CSD and CSX-based designs, higher the Fmod/Fsw ratio, higher is the number of flat spots and lesser is the width of flat spots. Hence, set Fmod/Fsw ratio to a maximum possible value while ensuring reasonable sensitivity.
Thus, the flat spots can be reduced and the undesirable consequences of gradual environmental variations can be overcome.