Route Internal Clock Out to a Pin in PSoC 6 – KBA224493

Author: XZNG         Version: *A



In PSoC® 6, how can I route the internal clock out to a pin for other purposes?



For all PSoC 6 parts, the output of CLK_HF [4] (or  CLK_HF [5]) can be routed out through P0[0] or P0[5]. All internal source clock (IMO, ECO, EXTCLK, BLE ECO, ILO, PLIO, WCO, Digital Signal) can be routed to CLK_HF[4] (or CLK_HF [5]) through internal clock path, so you can get any internal source clock directly (or 2/4/8 divided) from either the P0[0] or the P0[5] pin.

The method of routing the internal clock out to a pin in PSoC Creator is simple:

  1. Configure the required internal source clock to CLK_HF[4] and choose a suitable divider value.
  2. Drag a clock component and choose CLK_HF[4] as the source in the clock component.
  3. Drag a Digital Output pin component and assign P0[0] or P0[5] to the component. Connect the clock and pin component.


Figure 1. Clock Configuration and Placement in PSoC Creator

For PSoC 6 parts with UDB resource, there is another way to route CLK_HF[x] out to a pin through UDB/DSI resource. The output pin is not limited to P0[0] or P0[5] only, any GPIO pin is fine.


Figure 2 shows the TopDesign schematic.


Figure 2. Top Design Schematic

Note: In PSoC Creator, P0[0] and P0[5] are also dedicated EXT_CLK pins; if either P0[0] or P0[5] is used as EXT_CLK pin, the other pin can be used for clock output.