Author: XZNG Version: *A
In PSoC® 6, how can I route the internal clock out to a pin for other purposes?
For all PSoC 6 parts, the output of CLK_HF  (or CLK_HF ) can be routed out through P0 or P0. All internal source clock (IMO, ECO, EXTCLK, BLE ECO, ILO, PLIO, WCO, Digital Signal) can be routed to CLK_HF (or CLK_HF ) through internal clock path, so you can get any internal source clock directly (or 2/4/8 divided) from either the P0 or the P0 pin.
The method of routing the internal clock out to a pin in PSoC Creator is simple:
- Configure the required internal source clock to CLK_HF and choose a suitable divider value.
- Drag a clock component and choose CLK_HF as the source in the clock component.
- Drag a Digital Output pin component and assign P0 or P0 to the component. Connect the clock and pin component.
Figure 1. Clock Configuration and Placement in PSoC Creator
For PSoC 6 parts with UDB resource, there is another way to route CLK_HF[x] out to a pin through UDB/DSI resource. The output pin is not limited to P0 or P0 only, any GPIO pin is fine.
Figure 2 shows the TopDesign schematic.
Figure 2. Top Design Schematic
Note: In PSoC Creator, P0 and P0 are also dedicated EXT_CLK pins; if either P0 or P0 is used as EXT_CLK pin, the other pin can be used for clock output.