Maintain UART Baud Rate Stable when Peripheral Clock is Changed in PSoC 6 – KBA224500

Version 6

    Author: XZNG       Version: *A


    Translation - Japanese: PSoC 6 でペリフェラルクロックが変化しても UART のボーレートを安定に保つ - KBA224500 - Community Translated (JA)



    How can I keep the UART baud rate stable if the peripheral clock (Clk_Peri) is dynamically changed for low power designs in PSoC® 6?



    If you are using PSoC Creator, you can configure the UART baud rate in the component GUI, but per actual operation mechanism PSoC Creator™ assigns a clock UART_x_SCBCLK to UART according to the component setting. PSoC Creator calculates the suitable divider and configures the clock in the background. PSoC Creator performs these tasks when the Enable Clock from Terminal option of UART is not selected (the default option).


    However, when the Enable Clock from Terminal option is selected, a clock terminal appears on the component icon. It is your responsibility to calculate and configure the clock for UART. You can change the clock output dynamically using the APIs provided by the Clock Component. This provides you a chance to reconfigure and keep the UART clock stable when the source clock is changed.


    To decide the UART clock divider to be used before and after peripheral clock change, you can use the equation:


    UART clock divider = CLK_PERI/(UART Baud Rate * Oversample)




    CLK_PERI is the source clock for all programmable peripheral clock dividers


    If you are using ModusToolbox, use can use the following API to set the clock divider: Cy_SysClk_PeriphSetDivider(). You can refer to PDL documentation for more details on the function usage.