Control Area Network (CAN) Protocol Troubleshooting Guide for PSoC® - KBA224456

Author: harshadap_76         Version: *A

 

Question:

What are the general considerations while using a Control Area Network (CAN) Component and how can I troubleshoot different CAN issues?

 

Answer:

This document provides the general guidelines for using PSoC® CAN component. It documents the commonly reported issues and the debugging steps. This document could be used as troubleshooting guide for PSoC CAN.

 

1.  General Information.

1.1   CAN Conformance Test Reports.

1.2   Reference Documents and Links.

1.3   Example Projects.

1.4   Cypress Kits for developing CAN projects.

1.5   Comparison of CAN Component in different PSoC Families.

 

2.  Steps to Configure CAN Component.

2.1   Configuring CAN Component in PSoC Creator.

2.2   Guidelines on Hardware Connections.

2.3   Setting the Interrupt for Monitoring Error Events in CAN.

 

3.    Debugging CAN Issues.

3.1   CAN frames not Received.

3.2   CAN frame is not Transmitted.

3.3   Trimming WCO Causes Problem in Communication.

3.4   CAN did not Work with CY8CKIT-026.

3.5   Certain Nodes did not Receive or Transmit the CAN Messages.

3.6   PSoC Creator Throws a Clock Error in a CAN Project.

 

4.  Frequently Asked Questions.

 

 

1. General Information

CAN component is supported in PSoC 3, PSoC 5LP, PSoC 4100M, PSoC 4200M, PSoC 4200L, and PSoC 4100S Plus families. PSoC 4M and PSoC 4100S Plus have Automotive grade devices.

CAN component supports CAN2.0A and CAN2.0B protocol implementation and is ISO 11898-1 compliant. The higher libraries are not implemented in the CAN Component. You can build your own libraries over CAN. This document assumes that you have some basic familiarity with PSoC 3, PSoC 4, and PSoC 5lp devices and PSoC Creator™.

If you are new to these devices, see AN54181 - Getting Started with PSoC® 3, AN77759 - Getting Started with PSoC® 5LP, and  AN79953 – Getting Started with PSoC 4. If you are new to PSoC Creator, see the PSoC Creator home page.

 

1.1 CAN Conformance Test Reports

The CAN Component is certified by the C&S group GmbH based on the standard protocol and data link layer conformance tests. A complete certification report can be made available on request.

 

1.2 Reference Documents and Links

Go through the following documents before starting with CAN in PSoC:

    Here are some additional documents that you can read through:

 

1.3 Example Projects

PSoC Creator includes CAN basic and CAN full example projects for all supported devices. Follow the menu path, File à Code Example. In the Find Code Example window, select the PSoC family from the Device family dropdown list. Select CAN from the Filter by dropdown list. See Figure 1.

Figure 1. Selecting CAN examples in PSoC Creator

 

 

1.4 Cypress Kits for developing CAN projects

Following are the links to the PSoC prototyping kits for each family and to the Transceiver kits:

 

1.5 Comparison of CAN Component in different PSoC Families

The CAN component implementation in PSoC 3 and PSoC 5LP families is same. The implementation in PSoC 4 (PSoC 4M,
PSoC 4L, and PSoC 4S) families slightly differ from that of PSoC 3 and PSoC 5LP.

Table 1 lists the differences.

Table 1. Differences in CAN component implementation

Feature

CAN PSoC 3 and PSoC 5LP

CAN in PSoC 4M, PSoC 4L, and PSoC 4S Plus

Single Shot Transmissions

Not Available

Available

External loopback test modes

Not Available

Available

Selecting Data Byte Endianness

Not Available

Available

Interrupt when Rx is stuck at '0' (Dominant) for more than 11 consecutive bit times

Not Available

Available

Interrupt for RTR

Not Available

Available

Accessing Error Capture register

Not Available

Available

Save and Restore Config APIs

Available

Not Available.

 

Certain macros and registers for CAN component are different for PSoC 3, PSoC 5LP, and PSoC 4 families. See the Register Technical Reference Manual (TRM) and Architecture TRM of the respective PSoC family.

 

2. Steps to Configure CAN Component

 

2.1 Configuring CAN Component in PSoC Creator

See the Reference Documents and Links section before configuring the CAN Component. Follow these steps to configure the CAN Component in PSoC Creator:

  1. Make sure the clock settings are done in Project.cydwr à Clocks according to the settings mentioned in the respective reference documents. See step 2 in the Configuring CAN Component in Hardware section for more details.
  2. Drag and drop the CAN Component.
  3. Assign the CAN Tx and Rx pins to the appropriate ports.
  4. Configure the General tab in the CAN Component configuration.
  5. Configure the baud rate to the desired value. Select the appropriate BRP, TSEG, and SJW in the Component configuration.
  6. Configure the Rx buffer.
  7. Configure the Tx buffer.

 

2.2 Guidelines on Hardware Connections

Select the suitable CAN transceiver based on the range of supported baud rates, provision for listening mode, and so on. Some of the transceivers may require SPI to configure and initialize them.

For development stage, you can use CY8CKIT-026 CAN and LIN Shield Kit. Following are the guidelines for connecting the CY8CKIT-026 kit and the corresponding changes to be made in PSoC Creator:

  • Plug in CY8CKIT-026 to the base kit through the Arduino-compatible connectors. CY8CKIT-026 has two CAN transceivers: CAN1 and CAN2. Connect J3_10 (CAN_Rx) and J3_9(CAN_Tx) to the appropriate CAN_Rx and CAN_Tx of the transceiver (J19 – CAN1 or J9 – CAN2).
  • Enabling CAN transceivers depends on power configuration in CY8CKIT-026 kit. Note that only CAN2 is enabled if CY8CKIT026 kit is powered by baseboard (when pin1 and pin2 of jumper J20 of CY8CKIT-026 are connected to each other). In order to enable both the CAN transceivers, external power supply should be connected to shield kit which will power the baseboard too (pin 2-3 of J20 connected or pin 3-4 of J20 connected ). Figure 2 shows the schematic of jumper J20 in CY8CKIT-026 and the connection details. Make sure that you place the jumper at correct position based on CAN transceivers you are enabling.

                    Figure 2. Schematic and Connections Details of Jumper J20 in CY8CKIT-026

  • CAN clock tolerance should be ± 1.58% for baud rates up to 125 kbps and 0.5% for higher rates. For PSoC 4, CAN clock source is HFCLK and for PSoC 3 and PSoC 5LP, the clock source is BUS_CLK. Make sure that these clocks are derived from high accuracy clocks. Here are the options to use an accurate CAN clock for PSoC 4 CAN projects:
    • If a device runs on internal main oscillator (IMO), then it should be trimmed using external high accuracy watch crystal oscillator (WCO). IMO has a tolerance of ± 2%, which is beyond the CAN protocol specification. You should enable Trim with WCO option as shown in Figure 3. Make sure that WCO crystal (32 kHz) is mounted on the board and connected to the correct PSoC pins. To check the pins, see the respective PSoC device datasheet.

Figure 3. Trim With WCO

 

    • Instead of using IMO, use an external crystal or external oscillator as a clock source for PSoC which is within CAN clock tolerance limit. Make sure that external clock is connected to the specified pin in selected PSoC device. Figure 4

Figure 4. Enable external clock

 

 

  • In PSoC 3 and PSoC 5LP, IMO can be used when its value is 3 MHz. IMO can be used only for CAN baud rates up to 125 Kbps as its tolerance is ±1%. To achieve higher baud rates an external clock with ±0.5% tolerance is needed.

See AN60631 - PSoC® 3 and PSoC 5LP Clocking Resources and AN52701 - PSoC® 3 and PSoC 5LP - Getting Started with Controller Area Network (CAN) for more details.

  • If you are using a DB9 connector, make sure your cable is a direct connected cable.

See http://www.interfacebus.com/Can_Bus_Connector_Pinout.html for different types of cables. Figure 5 shows the CAN pins on a DB9 female connector.

Figure 5. DB9 Connector

 

2.3 Setting the Interrupt for Monitoring Error Events in CAN

Monitoring Error events in CAN help you to monitor the network and debug any issue observed while transmitting or receiving. It is the responsibility of the user code to handle the errors when they are triggered. The Interrupt tab of the CAN component lists the events that can trigger an interrupt when enabled.  CAN component has only one allocated ISR. For any kind of interrupt, only one ISR will be asserted. Hence, receive message event and error event will trigger the same ISR. You need to check the respective flag of CAN_INT_SR_REG and handle it in the code. This section explains how to handle error interrupts.

Enable the desired interrupt in CAN the configuration window. See Figure 6.

Figure 6. Enabling CAN interrupts

 

 

Once the interrupt is enabled, the corresponding macro in CAN.h will be set to 1.

For example, if you select Bit stuffing error detected in the configuration window and build the project, you will observe that #define CAN_STUFF_ERR is defined as 1 in CAN.h.

Following code in CAN.h is enabled:

#if (CAN_Rx_STUFF_ERR)

void CAN_BitStuffErrorIsr(void);

#endif /* CAN_Rx_STUFF_ERR */

 

When CAN_Rx_STUFF_ERR is defined as 1, the function void CAN_Rx_BitStuffErrorIsr(void) is enabled. This function can be used to handle bit stuff interrupt.

 

From the code snippet, include the code following the comment /* `#START BIT_STUFF_ERROR_ISR` */ in CAN_INT.c.

void CAN_Rx_BitStuffErrorIsr(void)

    {

        /* Clear Stuff Error flag */

        CAN_Rx_INT_SR_REG = CAN_Rx_STUFF_ERROR_MASK;

        /* `#START BIT_STUFF_ERROR_ISR` */

        //Place your code here

        /* `#END` */

        #ifdef CAN_Rx_BIT_STUFF_ERROR_ISR_CALLBACK

CAN_Rx_BitStuffErrorIsr_Callback();

        #endif /* CAN_Rx_BIT_STUFF_ERROR_ISR_CALLBACK */

}

 

You can add code to handle bit error in the ISR routine or include bit error handling in the callback function CAN_Rx_BitStuffErrorIsr_Callback(). To enable the callback function, add following macro in header file cyapicallbacks.h:

 

#define CAN_Rx_BIT_STUFF_ERROR_ISR_CALLBACK

 

This method can be referred for every interrupt that is enabled in the CAN configuration window. This helps in debugging the project and the CAN network.

 

3. Debugging CAN Issues

This section covers some common issues observed in CAN and the steps to debug these issues.

 

3.1 CAN frames not Received

  • Check if CAN ISR is triggered. If not, verify the following points in your source code:
    • Check if you have cleared the receive message flag in CY_ISR(CAN_ISR)

Add the following code to clear the receive message flag:

/* Clear Receive Message flag */

    CAN_INT_SR_REG = CAN_RX_MESSAGE_MASK;

 

    • If CAN interrupt is relocated to another file using CY_ISR_PROTO(ISR_CAN), assign the interrupt vector using CyIntSetVector(CAN_ISR_NUMBER, ISR_CAN). Make sure to clear the receive message flag. See section 4.2 Creating a Custom ISR in AN90799 - PSoC® 4 Interrupts
  • If CAN_1_SetOpMode()CAN_1_Start().
  • Check if the baud rates are set correctly in the CAN Component.
  • Verify if CAN clock source is correctly configured in *.cydwr. In case of IMO, check if IMO trim with WCO is enabled as shown in Figure 3.
  • Check if the WCO, external crystal, or external oscillator is correctly mounted on the board. See Steps to Configure CAN Component.
  • Do a dummy transmit and check the bit duration on the scope. Check if the bit duration is within the CAN tolerance.
  • Check if the transceiver is configured correctly and the connections are proper. Check if the transceiver supports the desired baud rate.
  • Verify if the transceiver pin connections are as per its datasheet.
  • Monitor the error event using the Interrupt method mentioned in Setting the Interrupt for Monitoring Error Events in CAN. For any kind of error, if the node is unable to recover by itself, the error counter will increase and reach the bus-off error.

 

Following are the errors that might occur while receiving CAN messages and the checks you can perform for each error:

    • Stuff error: Check the crystal or oscillators. For IMO trim with WCO, check the WCO crystal.
    • CRC error: This error occurs mostly at the transmitter and the network will be able to recover. Check the data on the bus and transmitted data.
    • Form error: Check the hardware connections. Check if CAN-H or CAN-L line are stuck at 0 (gnd). Check if there is any external ESD event which is changing the bit logic.

 

3.2 CAN frame is not Transmitted

Check if Bit, Ack or Bus-off error is triggered. If yes, then:

  • Check if termination resistor is mounted on the bus.
  • Check the Bus connection.
  • Verify if CAN clock source is correctly configured in *.cydwr. In case of IMO, check if IMO trim with WCO is enabled as shown in Figure 3.
  • Check if the WCO, external crystal, or external oscillator is correctly mounted on the board. See Steps to Configure CAN Component.
  • Check if the baud rates are set correctly in the component.
  • If CAN_1_SetOpMode()CAN_1_Start().
  • Do a dummy transmit and check the bit duration on the scope. Check if measured bit time is within the CAN tolerance.
  • Check if the transceiver is configured correctly and the connections are proper. Check if the transceiver supports the desired baud rate. Verify if the transceiver pin connections are as per its datasheet.

 

3.3 Trimming WCO Causes Problem in Communication

Make sure that WCO is mounted onboard. Set the correct values for IMO trimming with WCO as shown in Figure 3.

To check if WCO is properly trimming IMO, HFCLK can be routed to a pin when WCO trim is enabled. This will help to check if IMO tolerance is within the CAN clock specification after trimming. Note that this procedure is only possible for devices with digital signal interface (DSI). To know whether the device has DSI, check respective Architecture TRM or device datasheet.

Follow these steps to route HFCLK to a pin:

  1. Drag and drop the Digital output pin and make sure that hardware connection is disabled as shown in Figure 7.

Figure 7. Pin Configurations

  

 

2.  Go to the Clocking tab and assign the following parameters:

    • In clock
    • In clk en
    • In reset
    • Out clock
    • Out Clk en

Figure 8. Clocking Settings

 

3. Drag and drop a clock component and set:

    • Initially align to: HFCLK
    • Frequency: 24 MHz

Figure 9. Clock Component Settings

 

4. Connect the clock component to the pin as shown in Figure 10.

Figure 10. Connect Clock Component to Pin

 

This helps to monitor IMO clock over oscilloscope.

 

3.4 CAN did not Work with CY8CKIT-026

If the shield is connected to a custom board or if the shield is not placed on top of any Cypress Arduino compatible kits, the following jumper settings are required for CAN:

  • CAN 1 Transceiver requires Pin5 (V3.3) on J1 of Arduino header connected to 3.3 V or 5 V
  • CAN 2 Transceiver requires Pin7 (P4 VDD) on J1 of Arduino header connected to 3.3 V or 5 V

Note that CAN1 transceiver supports baud rates up to 125 Kbps. If the baud rate is higher, then use CAN2 transceiver and populate jumper J10 to add the termination resistor. See CY8CKIT-026 CAN and LIN Shield Kit Guide.

 

3.5  Certain Nodes did not Receive or Transmit the CAN Messages

Always check the CAN Tx and Rx data on oscilloscope. There are chances of stuff error whenever a CAN message is not received or transmitted (See CAN frames not received). If the IMO is not trimmed or CAN clock is incorrect due to WCO crystal or layout, then the baud rate will not meet the bit time requirement. See section 8 Crystal Analysis for WCO in AN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques while selecting and mounting WCO.

 

3.6 PSoC Creator Throws a Clock Error in a CAN Project

Figure 11 shows the clock error that PSoC Creator throws in a CAN project.

Figure 11. Clock Error

The CAN source clock is HFCLK. SYSCLK must be equal to or faster than all other clocks in the device that are derived from HFCLK. Make sure Sysclk is equal to or higher that the CAN source clock.

 

4. Frequently Asked Questions

  1. How can I set a filter to accept a range of IDs or one ID?

Here are the steps to configure a mail box.

To accept an ID in Full CAN:

    1. Right-click the CAN Component and select Configure.
    2. Go to the Receive Buffers tab.
    3. Select the mailbox.
    4. Select Full CAN.
    5. Enter the ID that you want to filter in the ID column.

   For more information, see section 17.5.2 Acceptance Filter in PSoC 4100M/4200M Family PSoC 4 Architecture TRM.

   To accept an ID in Basic CAN:

    1. Right-click the CAN Component and select Configure.
    2. Go to the Receive Buffers tab.
    3. Select the mail box.
    4. Select Basic CAN.
    5. In main.c declare a variable of type CAN_RX_CFG.

CAN_RX_CFG rxMailbox;

 

For basic CAN configuration, the ID is set using acceptance mask register (AMR) and acceptance code register (ACR). Each mail box has its own AMR and ACR. The following is the AMR and ACR representation:

      • [31:3] – Identifier (ID[31:21] – identifier when IDE = 0, ID[31:3] - identifier when IDE = 1)
      • [2] – IDE,
      • [1] – RTR
      • [0] – N/A

The structure, CAN_RX_CFG, has four elements: rxmailbox, rxamr, rxacr, and rxcmd.

For setting the ID, set the acceptance filter by modifying amr and acr for a mailbox. For example, to set 0x001 as ID for the mailbox, set amr and acr as shown here:

rxMailbox.rxmailbox = 0;

rxMailbox.rxamr= 0x001FFFF9u; //IDE=0 (Standard ID, RTR=0,Bit[31:21]=0 to AMR register

/* writing 1 to a bit in amr register makes respective acr bit as don't care. If 0 the/n corresponding bit in acr register is checked for filtering. */

rxMailbox.rxacr = 0x00200000u; // Write ID = 0x001 to Bit[31:21] (most significant 11 bits of this register for standard ID).

 

To accept a range of IDs, use the basic mailbox. To set up the mailbox to receive a range of IDs of 0x180–187, IDE = 0 (cleared), RTR = 0 (cleared), set the values in Table 2 for the AMR and ACR registers.

Table 2. Values in AMR and ACR Registers

ACR Value

AMR Value

Comments

ACR[31:21] = 0x180

AMR[31:21] = 0x7

Last 3 bits of ID [31:21] are set to don’t care to receive IDs in the range of 0x180 to187. So, AMR is set to 0x7.

ACR[20:3] = 0x0 (don't care)

AMR[20:3] = 0x3FFFF (all ones)

Don’t care for 11 bit identifiers

ACR[2] = 0

AMR[2] = 0

IDE = 0

ACR[1] = 0

AMR[1] = 0

RTR =0

ACR[0] = 0

AMR[0] = 0

N/A

 

rxMailbox.rxamr= 0x007FFFF9u; //Writing to AMR register

rxMailbox.rxacr=0x30000000u; //180<<21

 

Thus, the AMR register can be used to accept a certain range of IDs.

 

   2. How can a CAN Rx ID be changed dynamically? How can the AMR and ACR registers be modified?

To assign ID dynamically, set the Acceptance filter of the CAN Component. For more information, see section 17.5.2 Acceptance Filter PSoC 4100M/4200M Family PSoC 4 Architecture TRM. Figure 11 shows the acceptance filter in CAN. In case of standard (11-bit) Identifier, bit numbers 21 to 31 of the AMR and ACR registers are used for filtering. In case of extended (29-bit) Identifier, bit numbers 3 to 31 of the AMR and ACR registers are used.

In Figure 12, the message frame has 11-bit Identifier, and requires the 9th and 10th bits to be don’t care (can be 0 or 1). You need to write 1 in the AMR register for these two bits. Hence in Figure 12, bits 30 and 29 are set to 1.

Figure 12. Acceptance Filter in CAN

  

For example, if you need to change the standard ID to 0x011, the value of bits 31 to 21 in the ACR register should be set to 0x011. For acceptance filter to check ACR register, set the corresponding bits of the AMR register to 0s.

Following code snippets can also be used for respective PSoC families.

 

PSOC 3 and PSoC 5LP Families

For Standard ID:

/*0x110 is new ID assigned in the below code, you can assign your own ID */

                         uint8 result = CAN_FAIL;

uint32 temp_amr;

uint32 temp_acr;

/* obtain necessary value to put in AMR (Bit[31;21]is Mask set to 0 for ID, Bit[20:3]=1, Bit2(IDE)=0, Bit1 RTR=0,Bit0=N/A */

temp_amr = ((uint32)0x0u << 21u) | ((uint32)0x3FFFFu << 3u);

/* obtain necessary value to put in ACR (Bit[31;21]is ID=0x110, Bit[20:3]=1, Bit2(IDE)=0, Bit1 RTR=0,Bit0=N/A */

temp_acr = ((uint32)0x110u << 21u) | ((uint32)0x3FFFFu << 3u); 

/*Writing to AMR reg and check if success*/

if (CAN_RXRegisterInit((reg32 *)&CAN_RX[1].rxamr, temp_amr) == CYRET_SUCCESS)

{

/*Writing to ACR reg and check if success*/

      if (CAN_RXRegisterInit((reg32 *)&CAN_RX[1].rxacr, temp_acr) == CYRET_SUCCESS)

      {

          result = CYRET_SUCCESS;

      }

}

For Extended ID:

  uint8 result = CAN_FAIL;

  uint32 temp_amr;

  uint32 temp_acr;         

  temp_amr = ((uint32)0x0u << 3u); /* obtain necessary value to put in AMR (Bit[31;3] are zero */

  temp_acr = ((uint32)0x110u << 3u); /* obtain necessary value to put in ACR (Bit[31;3] is ID 0x110, */

  temp_acr |= (uint32)0x04u; /* Bit2(IDE)=1*/

  if (CAN_RXRegisterInit((reg32 *)&CAN_RX[1].rxamr, temp_amr) == CYRET_SUCCESS)

  {

      if (CAN_RXRegisterInit((reg32 *)&CAN_RX[1].rxacr, temp_acr) == CYRET_SUCCESS)

      {

          result = CYRET_SUCCESS;

      }

  }

    }

Here the line temp_acr = ((uint32)0x110u << 3u); stores the ID in temp_acr. The API call CAN_RXRegisterInit((reg32 *)&CAN_RX[1].rxacr, temp_acr)  writes this ID to the ACR register.

 

PSoC 4 Families:

#define AMR_1 (0x001FFFF9) /* AMR (Bit[31;21]is Mask set to 0 for ID, Bit[20:3]=1, Bit2(IDE)=0, Bit1   RTR=0,Bit0=N/A*/

#define ACR_1 (0x00600000) /* ACR (Bit[31;21]is ID=0x110, Bit2(IDE)=0, Bit1   RTR=0,Bit0=N/A*/

 

CY_SET_REG32((reg32 *) (&CAN_Rx_RX[0].rxamr),AMR_1);

CY_SET_REG32((reg32 *) (&CAN_Rx_RX[0].rxacr),ACR_1);

 

   3. How can bus-off conditions be handled?

Bus-off condition is when the error counter of the CAN controller reaches 255; that is, the controller was unable to recover when errors occurred. This will trigger the bus-off ISR and you can set a flag in the ISR. For details on configuring ISR, see Setting the Interrupt for Monitoring Error Events in CAN. The CAN controller should be restarted in case of Bus-off condition. The CAN Component has auto restart feature after bus-off as shown in the Figure 13.

Figure 13. Bus-off Restart

  

You can also restart in the firmware using the following code snippet.

CAN_Start();

CyIntSetVector(CAN_ISR_NUMBER, ISR_CAN);

 

It is not required to call CAN_Stop().

 

   4. How can the baud rate be changed dynamically?

Use the CAN_SetPreScaler () and CAN_SetTsegSample () APIs to set prescaler, and Tseg, sjw values respectively. Make sure that CAN messages are not sent or received when baud rate is changed in firmware.   

Tseg1, Tseg2, SJW, and BRP should be modified to change the baud rate. These values will be decided based on clock frequency and sample point.

To find these values for a given clock and baud rate, see the table in the Timing tab of the Component configuration window.  See Figure 14 for 125 Kbps baud rate.

 

Figure 14. Timing Tab in CAN Configuration Window

  

In Figure 14, for a 24-MHz source clock and 125 Kbps baud rate, the table suggests a list of BRP and Tseg values. Choose a value based on the network requirement and sample point one. In Figure 14, for sample point 81.3, the values are: BRP = 11, Tseg1 = 12, Tseg2 = 3, and SJW = 3.

Here is the code snippet that sets the baud rate based on the values in the Timing tab.

#define BITRATE           (11u) //BRP

#define TSEG1             (12u - 1u) //TSEG1

#define TSEG2             (3u - 1u) //TSEG2

#define SJW               (3u - 1u) //SJW

#define SAMPLING_MODE     (0u) //number of sample point

if (CAN_SetPreScaler(BITRATE) == CYRET_SUCCESS) //Set the BRP value

{

CAN_SetTsegSample(TSEG1,TSEG2,SJW,CAN_SAMPLING_MODE) == CYRET_SUCCESS) //Set TSEG1,TSEG2,SJW and sampling mode.

}

 

   5.  How can CAN_SetPreScaler () and CAN_SetTsegSample () be used?

To set Tseg1, Tseg2, and SJW, pass the values one less than the desired value to the CAN_SetTsegSample () function. To set BRP pass its value to the CAN_SetPreScaler () function.

For example, to set Tseg1 = 11, Tseg2 = 4, and SJW = 4, sampling mode = 1 (see the CAN component datasheet for details), then pass following values:

CAN_SetTsegSample(10,3,3,1);

 

In PSoC Creator, check whether the CAN.h file has following #defines:

            #define CAN_CFG_REG_TSEG1

#define CAN_CFG_REG_TSEG2  

#define CAN_CFG_REG_SJW

 

These #defines are 'Value-1'. These #defines are by default passed to CAN_SetTsegSample in the CAN_Init() function. (See the CAN.c file).

 

   6.  What are the different oscillators required for CAN communication?

Table 3 lists the oscillators used in different devices and scenarios.

 

Table 3. Oscillators Available in Different Devices

 

Oscillator

PSoC 4200M, PSoC 4100M

PSoC 4100 S Plus

PSoC 3 and PSoC 5LP

IMO

 

 

ü  (IMO= 3 MHz, only for CAN baud rate up to 125 Kbps)

IMO with WCO

ü 

ü 

 

External Oscillator

ü 

ü 

ü  (DSI system clocks)

External MHz crystal

 

ü 

ü 

 

See Steps to Configure CAN Component for more details.

 

   7.  How can I Identify if the received message is an RTR message?

You can access the 21st bit of the CAN0_CAN_RX0_CONTROL register to check if RTR message is received. Whenever CAN receives a RTR message, this bit is set. See section 3.1.1 CAN0_CAN_RX0_CONTROL in PSoC 4100M/4200M Family PSoC 4 Architecture TRM.

 

The CAN0_CAN_RX0_CONTROL register is defined by the CAN_RX_REG macro. Hence, you can access the macro:

 

uint32 reg;

reg= (uint32)CAN_RX_REG;

 

You can then read the 21st bit of the register

 

   8.  How can the received message identifier be read?

Get the received message ID in PSoC 3 and PSoC 5LP.   

For extended ID:

(CY_GET_REG32(CAN_RX_ID_PTR(i)) >> CAN_SET_TX_ID_EXTENDED_MSG_SHIFT)

For standard ID:

(CY_GET_REG32(CAN_RX_ID_PTR(i)) >> CAN_SET_TX_ID_STANDARD_MSG_SHIFT)

       Get the received message in PSoC 4:

For extended ID:

CAN_GET_RX_IDE(i)

For standard ID:

CAN_GET_RX_ID(i)

   9.  How can I identify if a mailbox has received a message?

Each mailbox has an ID. In PSoC 4, the CANn_BUFFER_STATUS register gives the status of each mailbox (0: when the mailbox is empty and 1: if there are unread messages in the mailbox).

See Table 4 for the buffer status register.

Table 4. CAN Buffer Status Register

RxMessage and TxMessage Buffer Status
Address: 0x402E0008

        Retention: Retained

                                                                

Bits

7

6

5

4

3

2

1

0

SW   Access

R

R

R

R

R

R

R

R

HW   Access

RW

RW

RW

RW

RW

RW

RW

RW

Name

RX7_MSG_AV

RX6_MSG_AV

RX5_MSG_AV

RX4_MSG_AV

RX3_MSG_AV

RX2_MSG_AV

RX1_MSG_AV

RX0_MSG_AV

                                                                

Bits

15

14

13

12

11

10

9

8

SW   Access

R

R

R

R

R

R

R

R

HW   Access

RW

RW

RW

RW

RW

RW

RW

RW

Name

RX15_MSG_AV

RX14_MSG_AV

RX13_MSG_AV

RX12_MSG_AV

RX11_MSG_AV

RX10_MSG_AV

RX9_MSG_AV

RX8_MSG_AV

                                                           

Bits

23

22

21

20

19

18

17

16

SW   Access

R

R

R

R

R

R

R

R

HW   Access

RW

RW

RW

RW

RW

RW

RW

RW

Name

TX7_REQ_PEND

TX6_REQ_PEND

TX5_REQ_PEND

TX4_REQ_PEND

TX3_REQ_PEND

TX2_REQ_PEND

TX1_REQ_PEND

TX0_REQ_PEND

                       

Bits

31

30

29

28

27

26

25

24

SW   Access

None

HW   Access

None

Name

None   [31:24]

In PSoC 3 and PSoC 5LP, the CAN[0..0]_CSR_BUF_SR register provides the status of the mailbox. See the register detail in Table 5.

 

Table 5. CAN0_CSR_BUF_SR

  BUF_SR

A

Reset: Domain reset for non-retention flops [reset_all_nonretention] 

Register: Address

CAN0_CSR_BUF_SR: 0x4000A008

 

Bits

15

14

13

12

11

10

9

8

SW Access:Reset

R:0

R:0

R:0

R:0

R:0

R:0

R:0

R:0

HW Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Retention

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

Name

rx_msg15

rx_msg14

rx_msg13

rx_msg12

rx_msg11

rx_msg10

rx_msg9

rx_msg8

 

Bits

7

6

5

4

3

2

1

0

SW Access:Reset

R:0

R:0

R:0

R:0

R:0

R:0

R:0

R:0

HW Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Retention

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

Name

rx_msg7

rx_msg6

rx_msg5

rx_msg4

rx_msg3

rx_msg2

rx_msg1

rx_msg0

 

Bits

31

30

29

28

27

26

25

24

SW Access:Reset

NA:00000000

HW Access

NA

Retention

NA

Name

RSVD

 

Bits

23

22

21

20

19

18

17

16

SW Access:Reset

R:0

R:0

R:0

R:0

R:0

R:0

R:0

R:0

HW Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Retention

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

NONRET

Name

tx_msg7

tx_msg6

tx_msg5

tx_msg4

tx_msg3

tx_msg2

tx_msg1

tx_msg0

 

Use the CAN_BUF_SR_REG macro to access these registers. This macro is applicable for PSoC 3, PSoC 4, and PSoC 5LP devices.

                                                                

Bits

7

6

5

4

3

2

1

0

SW   Access

R

R

R

R

R

R

R

R

HW   Access

RW

RW

RW

RW

RW

RW

RW

RW

Name

RX7_MSG_AV

RX6_MSG_AV

RX5_MSG_AV

RX4_MSG_AV

RX3_MSG_AV

RX2_MSG_AV

RX1_MSG_AV

RX0_MSG_AV

 

In PSoC 3 and PSoC 5LP, the CAN[0..0]_CSR_BUF_SR register provides the status of the mailbox. See the register detail in Table 5.Use the CAN_BUF_SR_REG macro to access these registers. This macro is applicable for PSoC 3, PSoC 4, and PSoC 5LP device

 

   10. Is there an example for CAN bootloader?

PSoC 5LP CAN bootloader sample project is available here. You can see this example for creating CAN Bootloader in PSoC 3 and PSoC 5LP.

For PSoC 4, use PSoC 4 Bootloader Component with custom communication (See the Bootloader component datasheet). See CAN_BOOT.c in the bootloader sample project and use the PSoC 4 CAN component APIs.

 

   11.  Does PSoC CAN Component support triggering DMA by CAN interrupt?

PSoC 4M and PSoC 4L families do not support CAN interrupt triggering DMA. PSoC 4100S Plus family supports CAN interrupt triggering DMA.

 

   12.  How do I link CAN mailboxes?

When multiple messages are received, the current message is overwritten.

To avoid overwriting, link the CAN mailboxes using the link flag (bit number 6 of RX_CMD register) of the mailboxes. To link mailbox 1 to mailbox 2, set the link flag of mailbox1. To link mailbox 2 to mailbox 3, set the link flag of mailbox 2 and so on.

The easiest way to link is to use the CAN_SET_RX_LINKING(i) macro, where i is the respective mailbox.

After starting CAN, you can use the macro as:

CAN_SET_RX_LINKING(0);

CAN_SET_RX_LINKING(1);

.

.

.

CAN_SET_RX_LINKING(14);

 

Do not set this bit to the last mailbox, that is the 15th mailbox as there are no mailbox to link.

After linking the mailboxes, the message will reside in mailboxes sequentially (first message in mailbox0, second message in mailbox1, and so on). You can access messages from the respective mailbox. Make sure that all mailboxes have same the AMR and ACR settings.

To write to the macro CAN_SET_RX_LINKING(i), write protect bit of command register should be cleared. CAN_CLEAR_RX_WNPL() is used to clear the write protect bit of command register and CAN_SET_RX_WNPL() is used to set this bit.

For more details, see the  CAN component Datasheet, Architecture TRM, and Register TRM of the corresponding device.

 

   13. The user code added in CAN_TX_RX_func.c gets deleted when the mailbox is renamed. How can this be handled?

When the mailbox is renamed, the CAN_TX_RX_func.c file is regenerated and the custom code is disabled.

The workaround is to copy the custom code before renaming the mailbox. To copy the custom code

    1. Rename the mail box.
    2. Build the project.
    3. Place the code.
    4. Rebuild the project.

 

   14.  Does the CAN Component support vector stack?

There is a vector CAN-compatible Component for PSoC 3. You should use the Vector CAN Component for PSoC 3 along with the driver provided by Vector. See the device datasheet for more details.

The Vector CAN Component is not available for PSoC 5LP and PSoC 4. However, you can build your own stack in these devices.

 

   15. Does PSoC support two CAN blocks in a device?

PSoC 3, PSoC 5LP, and PSoC 4100S Plus have only one block. PSoC 4L and PSoC 4M support two blocks.

 

   16.  Do you have a J1939 library example project?

No. J1939 example project is not available.

 

   17.  Do you have On Board Diagnostics (OBD) library with the CAN Component?

OBD library is not available with the CAN Component.

 

   18.  Why is it impossible to assign CAN ID as 0x1FFFFFFF in the CAN Component?

According to the CAN protocol, the seven most significant bits of a CAN message ID cannot be all recessive, hence the range of CAN message ID is from 0x000 to 0x7EF for standard 11-bit identifier and to 0x1FBFFFFF for an extended 29-bit identifier. Hence, the CAN Component does not accept 0x1FFFFFFF.

 

   19.  How is it possible to receive more than 8 bytes without losing the previous bytes in the CAN buffer?

See the question How do I link CAN mailboxes.

 

   20.  Is there any error counter for CAN errors and what if the counter expires?

Yes, CAN 2.0 specifies an error counter. The CAN_GetTXErrorCount() and CAN_GetRXErrorCount() APIs return the error count for Tx and Rx respectively. If the error counter reaches 255, the CAN node is not allowed to transmit. This is called bus-off error. The CAN controller should be reset after a bus-off error.

 

   21.  Why does CAN transmit continuously even if CAN_SendMessage is called only once?

As per the CAN protocol, CAN will transmit data and check for ACK. If the node does not receive any ACK, then it will increase the error counter by eight and retransmit. This will continue till CAN receives ACK or it triggers the bus-off error. Hence even if you call CAN_SendMessage only once, you will observe continuous messages. If message retransmission is not desirable, use single shot transmission mode. In this mode, messages will not be retransmitted even if there is no ACK. This is supported in
PSoC 4 and not in PSoC 3 and PSoC 5LP.

See Figure 15 for enabling single shot transmission on CAN configuration window.

Figure 15. Enabling Single Shot Transmission (SST) in CAN Configuration Window

  

   22.  How can I wake up PSoC from Hibernate mode using CAN message?

CAN Component cannot wake up PSoC from Hibernate mode. However, CAN Rx pin can be configured as an interrupt pin to wake up the device:

    1. Right-click the Rx pin and select Configure.
    2. Go to the Input tab
    3. Select Interrupt as Falling edge.
    4. An IRQ terminal is seen on the Rx pin; connect the ISR Component to that Rx pin.

See the following application notes for low power modes:

While waking up the device from Hibernate mode or other low power modes, a dummy frame should be sent. Actual data transmission should be initiated only after the device wakes up.

 

   23.  Is CAN Component supported using Universal Digital Blocks (UDBs)?

No. CAN Component with UDBs is not feasible.

 

   24. Is there a CAN-open library with CAN Component?

No. There are no examples with CAN-open library.

 

   25.  Is CAN FD supported in PSoC?

No. Currently, PSoC does not support CAN FD . However, this is under consideration for future Automotive PSoC devices.