Author: ZhiF_31 Version: **
Translation - Japanese: NORフラッシュの初期アクセス時間とページアクセス時間 - KBA224033 - Community Translated (JA)
What is Access Time in NOR Flash?
Compared to NAND flash, one of the advantages of NOR flash is the ability to do fast random-access reads. This property means that high read speed can be maintained even if the address changes for every read access. In Parallel NOR flash devices, when the host system selects the device by driving CE# (Chip Enable) low, and if the WE# (Write Enable) is high at that moment, a random read access is started. The host can present any address value on the address lines, after certain time, while OE# (Output Enable) is low, the data for the requested word will be driven out on the data lines. The time between “address stable” to “valid data” is defined as “Initial Access Time”, tACC. Figure 1 shows the definition of tACC.
Figure 1. Definition of tACC
Initial Access Time is an important parameter in NOR flash memory products. It shows how quickly the device can drive out the first word after being selected. As a result, the smaller the initial access time, the faster the read speed.
Figure 1 shows another parameter, tPACC. It is called Page Access Time. If a Parallel NOR device supports Page Read, the host can keep CE# low after the first data is driven out, and change only the low address lines to read another address within a page. The page size is defined in the datasheet of the flash device. The requested data will appear after tPACC. Typically, tPACC is much shorter than tACC; therefore, by using page read timing for on-page reads, the system can achieve an even better-read throughput. See KBA219028 for more details on Page Access Time.
In SPI NOR flash, the interface is different, but the access time concept remains because internally, the memory technology is the same as for parallel NOR. When a read command is entered, after the address cycle, the device will take a similar amount of time, i.e. Initial Access Time, to make the data available to be read. This is the reason for Read Latency parameters in SPI NOR flash.
SPI interface is driven by SPI Clock to satisfy the Initial Access Time depending on the clock frequency; so, different numbers of dummy cycles are needed. For a constant access time, as clock speed increases, more dummy cycles are required to provide the correct initial access time.
For more information about configuring read latency in SPI NOR flash, see KBA219110.