Change S25FL064L from Default Serial SDR Mode to Quad or QPI Mode - KBA222445

Version 2

    Version: **

     

    Question:

    How do I change S25FL064L from the default SDR mode to Quad I/O Mode or QPI mode?

     

    Answer:

    Quad_NV Bit (CR1NV[1]):

    The Quad Data Width (Quad_NV) Bit is located within Configuration Register-1 NV, bit-1 (CR1NV[1]), and setting CR1NV[1] = 1 configures the flash into Quad Input / Output (QIO) mode.  This enables the flash to recognize and accept Dual and Quad output (1-1-2 and 1-1-4) commands, as well as Dual and Quad Input / Output (1-2-2 and 1-4-4) commands. Upon power on, bit values of CR1NV[7:0] are copied to CR1V[7:0] to set the default values for CR1V[7:0].

     

    QPI_NV Bit (CR2NV[3]) :

    The Quad Peripheral Interface (QPI_NV) Bit is located within Configuration Register-2 NV, bit-3 (CR2NV[3]), and setting CR2NV[3] = 1 configures the flash to boot up immediately in QPI mode.  In QPI mode, the instruction, address and data are transferred in 4-bit widths (4-4-4).  Upon power on, the bit values of CR2NV[7:0] are copied to CR2V[7:0] to set the default values for CR2V[7:0].

     

     

    Programming Quad_NV Bit (CR1NV[1]) = 1  and  QPI_NV Bit (CR2NV[3]) :

     

    1). Initiate the WREN (05h) command (automatically sets WEL Bit equal to ONE (SR1V[1] = 1).

     

    ** NOTE : The Write Enable for Volatile Registers (WRENV : 50h) command does not set the SR1V[1] WEL bit equal to “ONE”.

     

    2). Initiate the WRR (01h) command; input “02h” (for SR1NV[1]); input “02h” (for CR1NV[1]); input “68h” (for CR2NV[3]); CR3NV may remain as default values.

    Newly programmed Non-volatile register bit values :

    • SR1NV  =  02h  (programs WEL_D bit-1 = 1)
    • CR1NV  =  02h  (programs Quad_NV bit-1 = 1)
    • CR2NV  =  68h  (program QPI_NV bit-3 =1 : optional if QPI 4-4-4 protocol is required)
    • CR3NV  =  78h (may remain as default 78h, if no changes to Wrap and Latency settings) 

     

    Upon Power On Reset (POR), hardware reset, or software reset, non-volatile (NV) register bit values are copied to the volatile register to set the default values of the volatile register.  However, it is important to note that Status Register-2 (SR2V) does not have any user programmable non-volatile bits, and all defined bits are volatile read-only status. The default value of the SR2V bits upon power-on is “0”, but the status value is set by hardware.  Whenever non-volatile registers are erased and reprogrammed with new bit values, the volatile registers are updated with the same new bit values, respectively.

     

    Volatile register bits assumes non-volatile register bit values :

    • SR1V  =  02h (WEL_D bit-1 = 1, set by WREN : 05h command)
    • CR1V  =  02h (Quad I/O mode bit-1 = 1)
    • CR2V  =  68h (QPI bit-3 =1 : QPI 4-4-4 protocol is enabled)

    “X”  =  Don’t care;  CR1V[1] bit can be either “1” or “0”.  When CR2V[3] = 1, the QPI mode is active, and operates independently regardless

    of the setting of CR1V[1]. 

     

     

    Reference :

    URL to S25FL064L datasheet :

        http://www.cypress.com/file/316661/download