Advance Output Clock with respect to Input Reference Clock Using CY27410 - KBA223753

Version 10

    Version: **

     

    Question:

    How do I advance the output clock with respect to the input reference clock?

     

    Answer:

    Consider a scenario where, in your design, you have two independent blocks and their data is used in the next block. The data from the two previous blocks may have some skew, and may need synchronization. In such a situation, you may need to tune the clocks of the two blocks, effectively changing the availability of the data for the next block.

    Advancing the clock output with respect to the input reference can be achieved with a PLL-based design, which can also introduce a programmable delay into the clock output or equivalently advance the output clock with respect to reference input clock.

    Figure 1 shows an example of this implementation using Cypress’ CY27410 family of clock generators.

     

    Figure 1. Output Clock Fed-back as Input to PLL

    The DLY block can be programmed for delay of 0–4 cycles, where one cycle is (fcvo) / 2, where fcvo is the VCO block frequency in the PLL. These options are available while generating the configuration using ClockWizard 2.1 or later. The suggested approach is to have the PLL lock onto the highest delay output so that the output-channel with lower delay will come early in time.

     

    For CY27410, consider OUT11 as your reference output, with delay multipliers taking values in the range {0x, 1x, 2x, 3x, 4x} with changing the profile number for frequency select (FS) in the range {100, 011, 010, 001, 000}, while keeping the delay of the OUT14 at constant and at highest multiplier values of 4x-cycles.

     

    Figure 2. range of Clock Advancement Achievable Through Changing Profile

     

    Feedback (OUT14)

    Ref CLK (OUT11)

    Delay Achieved

    (w.r.t. Feedback, ∆d)

    FS000

    x4

    x4

    0 units

    FS001

    x4

    x3

    -1 units

    FS010

    x4

    x2

    -2 units

    FS011

    x4

    x1

    -3 units

    FS100

    x4

    x0

    -4 units

     

    Example Configuration:

    1. Reference input 60 MHz, applied at IN1
    2. PLL1 fVCO = 2400 MHz
    3. OUT14 (with delay multiplier x4) taken as feedback to PLL1 through IN2
    4. OUT11 will have a changing delay-multiplier with the changing FS profile

     

    Figure 3. Advancement of OUT11 Achieved with Respect to the Reference Input Clock

    Feedback (OUT14)

    Ref CLK (OUT11)

    Delay Achieved

    (w.r.t. Feedback, ∆d = 0.833 ns

    Advancement in OUT11 (Measured Value)

    FS000

    x4

    x4

    0 units

    0.062 ns

    See Figure 4

    FS001

    x4

    x3

    -1 units

    0.789 ns

    See Figure 5

    FS010

    x4

    x2

    -2 units

    1.647 ns

    See Figure 6

    FS011

    x4

    x1

    -3 units

    2.481 ns

    See Figure 7

    FS100

    x4

    x0

    -4 units

    3.313 ns

    See, Figure 8

     

     

    Figure 4. No Advancement (OUT11 at 4x, OUT14 at 4x) Profile FS000

     

     

    Figure 5. 1x Advancement (OUT11 at 3x, OUT14 at 4x) Profile FS001

     

     

    Figure 6. 2x Advancement (OUT11 at 2x, OUT14 at 4x) Profile FS010

     

     

    Figure 7. 3x Advancement (OUT11 at 1x, OUT14 at 4x) Profile FS011

     

     

    Figure 8. 4x Advancement (OUT11 at 0x, OUT14 at 4x) Profile FS100