Why does the S34MLxxG3 device require a 1-bit external ECC correction since it has an internal ECC engine?
Using the internal ECC function of the S34MLxxG3 device, the memory delivers corrected data to the page buffer. However, not having any external ECC correction capabilities leaves the buffer, system bus, and host buffer vulnerable to storage and transmission errors. Therefore, the host must have at least a 1-bit or 528-byte ECC correction capability for such protection. The function of the 1-bit external ECC is not protecting the bits during storage in NAND cells; it is only to protect the data buffers and bus from any additionally induced errors during data transmission.
You can place the ECC parity bits in the spare area as it is not used by the internal ECC engine.