When I lock a route in the analog editor (or perform a “lock all”), the next build produces an error like: “apr.M0086: Locked Route of Net_1 is shorted to \Comp_1:Net_1\ which is also locked”. How do I fix this error?
There is an issue with the way the warp synthesis tool applies directives. If a component implementation contains a wire with the same name as a wire at the top level of the design (in this example, both TopDesign and the implementation of Comp_1 contain a wire named “Net_1”), then a directive which is specified on the top-level wire may be also applied to the wire contained within the component implementation.
Rename the wire on the top schematic, so that its name does not match with that of any analog wire contained within another component in the design.
- Open the Analog DWR view and fully expand each component in the upper right pane.
- To unlock the route listed first in the error message, click the corresponding check box in the Locked column.
- Select a new unique name for the top-level wire. The component pane lists the wire names used in the implementations of components used in your design. You can refer to this list before choosing a unique name for the top-level wire
- Open TopDesign.cysch and right-click the wire that is to be renamed. If the component terminals involved are immediately adjacent to each other, you may need to drag one of them further away, so that a longer wire is drawn.
- Select Edit Name and Width.
- In the Signal Name window, clear the option Use computed name and width.
- Make sure that the Specify Full Name option is selected. In the text box below, replace “mywire_1” with the new unique name that you have selected.
- Click OK.
- Build the project.
- Return to the Analog DWR, and lock the newly renamed route as desired.