FX3 + FPGA + HelionVision ISP-Based Industrial Camera Reference Design – KBA222700

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Cypress provides a reference design for Industrial camera applications using FX3 and Lattice ECP5 FPGA with HelionVision ISP IP. This article documents the architectural, functional, and design details of this reference design for industrial camera systems. This reference design demonstrates a combined implementation of FX3 and Lattice ECP5 FPGA to interface an image sensor with the USB Host system.

 

The HelionVision ISP IP is implemented on the ECP5 FPGA to interface parallel/LVDS image sensors, process the image data, and stream via the GPIF-II interface of FX3.The following block diagram provides an overview of the high-level design of FX3 + ECP5 FPGA with HelionVision ISP IP supporting the camera interface.

 

Figure 1: System Block Diagram

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Hardware Details

The hardware consists of the main board with FX3, and ECP5 FPGA with an interface connector to attach the image sensor board. Reference design schematic and board files are attached along with this article. The main board is tested using Sony IMX-236 - HDR-60 Head-Board 1080p (3.1MP) image sensor board with Sunex Lens (Part No.: Sunex PN DSL945) connected using an M12 holder. The hardware main board has a USB Type-C connector to connect to Host systems. Boot options can be controlled using a switch that allows booting from external SPI flash or USB bootloader. The FX3 and FPGA firmware can be merged and saved in the external SPI flash.

Firmware Development

Cypress has tested the reference design hardware features using USB Video Class (UVC) framework implemented in FX3 with 1080p@30fps and 720p@30fps video resolutions and standard UVC video controls. The prototype system with a Sony IMX 236 image sensor is tested using ECP5 FPGA code developed by HelionVision and UVC firmware running on FX3. The FX3 firmware for the reference design uses the UVC architecture described in the application note AN75779– How to Implement an Image Sensor Interface Using EZ-USB FX3 in a USB Video Class (UVC) Framework. Note that this application note implements USB Video Class (UVC) Framework for an FX3 device. The GPIF II interface settings can be configured based on the Slave FIFO interface described in the application note AN65974- Designing with the EZ-USB® FX3™ Slave FIFO Interface. Refer to the Slave FIFO write operations section in AN65974 to understand the FPGA to FX3 interface. FX3 uses the standard Slave FIFO control signals available from the ECP5 FPGA to provide write access to internal FIFO buffers that can be committed to the Host system through the DMA channel present within FX3.

Note: Cypress can help users to develop FX3 firmware to support additional features. Contact Cypress Technical Support for additional board files, FX3 firmware and FPGA files to test prototype.