Use Cases that Disable Automatic ECC on the Mirrorbit 65nm Flash Family – KBA222872

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    Translation - Japanese: Cypress 65nm MirroeBit TechnologyのFlash Memoryに搭載されている内蔵ECC機能を無効にする使用方法 - KBA222872 - Community Translated (JA)



    What use cases disable Automatic ECC on the Mirrorbit 65nm Flash family?



    Cypress 65-nm MirrorBit NOR Flash designs have an automatic ECC feature that corrects every rare bit errors before the data leaves the flash. The ECC logic uses an Enhanced Hamming Code algorithm that can correct a single bit error per ECC Page. The ECC Page is 16 bytes of user data in SPI NOR devices and 32 bytes of user data in Parallel NOR devices. Each ECC Page of user data is associated with hidden ECC parity bits that are written when the user data is programmed. So long as the ECC parity bits are valid for any given ECC Page, the ECC logic is enabled for read accesses to that ECC Page. Once the ECC parity bits become invalid (see below), then a hidden non-volatile bit is programmed for that ECC Page that disables the ECC logic for all subsequent reads to that ECC Page, until the sector containing this ECC Page is erased.

    • Internal ECC is always enabled for an ECC Page so long as the system only writes once to that ECC page before the next sector erase. This is the best practice.
    • Writing two or more times to an ECC Page may disable the ECC logic on that page.

    The hidden ECC parity is computed based on the pattern of 1’s and 0’s that will be in the ECC Page after the programming operation completes. For the first write to an ECC page after the sector has been erased:

    • The correct parity bits can always be achieved solely by the 1 ->  0 bit transitions that are allowed during programming. So, after the first write, the ECC parity bits are valid and ECC is enabled for that page.

    If two or more writes are performed on this page, then if: 

    • The new parity bits can be achieved solely by the allowed 1 -> 0 bit transitions, the parity bits are valid and the ECC logic remains enabled.
    • The new parity bits can only be achieved with at least one forbidden 0 -> 1 bit transition, then valid ECC parity bits cannot be achieved solely by the allowed 1 -> 0 bit transitions and ECC is disabled for that page.

    So, while ECC may not be disabled on an ECC Page immediately upon the second write to that page, it is best to presume that ECC is always disabled after the second write.

    If your goal is to maximize the value of the internal ECC feature for your application, see the following application notes:

    AN200621 - Cypress GL-S and GL-T Mirrorbit® Flash Nonvolatile Memory Families – Automatic ECC
    AN200731 - Automatic ECC for Cypress 65-nm MirrorBit® Eclipse™ SPI Flash Nonvolatile Memory Families