PLL0 Clock Down Test of Clock Supervisor in Traveo™ S6J3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 Series MCUs - KBA222351

Version 2
Created by kbvtmp8 on Feb 8, 2018 10:51 PM. Last modified by kbvtmp8 on Feb 8, 2018 10:51 PM.
Version 2

    Version: **

     

    Question:

    In the PLL0 clock down test of clock supervisor, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs?

     

    Answer:

    According to the recommended clock settings of the target products (S6J3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 series), CPU cannot be reset when a CSV error of PLL0 occurs.

     

    When CSV error of PLL0 occurs, NMI (IRC0_NMIVA5) is notified to the CPU.

     

    The following figure shows the behavior of reset or NMI when CSV error of PLL0 occurs.

     

    Untitled.png

    For the target products, select SSCG0 for clock domain 0 or MCUC clock distribution. Note that PLLm cannot be selected.

     

    Therefore, when a CSV error of PLL0 occurs, the CPU is not reset and NMI is notified for the target products.