Translation - Japanese: Traveo S6J3XXXシリーズMCUのクロック監視のPLL0クロックダウンテスト - KBA222351 - Community Translated (JA)
In the PLL0 clock down test of clock supervisor in Traveo S6J3XXX series MCUs, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs?
According to the recommended clock settings of the target products, CPU cannot be reset when a CSV error of PLL0 occurs.
When a CSV error of PLL0 occurs, NMI (IRC0_NMIVA5) is notified to the CPU.
The following figure shows the behavior of reset or NMI when CSV error of PLL0 occurs.
For the target products, select SSCG0 for clock domain 0 or MCUC clock distribution. Note that PLLm cannot be selected.
Therefore, when a CSV error of PLL0 occurs, the CPU is not reset and NMI is notified for the target products.
Note: This KBA applies to the following series of Traveo MCUs: