PLL0 Clock Down Test of Clock Supervisor in Traveo S6J3XXX Series MCUs - KBA222351

Version: *A

 

Question:

In the PLL0 clock down test of clock supervisor in Traveo S6J3XXX series MCUs, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs?

 

Answer:

According to the recommended clock settings of the target products, CPU cannot be reset when a CSV error of PLL0 occurs.

When a CSV error of PLL0 occurs, NMI (IRC0_NMIVA5) is notified to the CPU.

The following figure shows the behavior of reset or NMI when CSV error of PLL0 occurs.

Untitled.png

For the target products, select SSCG0 for clock domain 0 or MCUC clock distribution. Note that PLLm cannot be selected.

 

Therefore, when a CSV error of PLL0 occurs, the CPU is not reset and NMI is notified for the target products.

 

Note: This KBA applies to the following series of Traveo MCUs:

  S6J3300

  S6J3350

  S6J3360

  S6J3370

  S6J3400

  S6J3510