Are there any timing limitations when using the Smart IO component?
When using the Smart IO’s Data Unit (DU) in certain configurations, it is possible to give the DU a short load pulse that does not encompass the rising edge of the clock. This results in DU operations not being executed. This is particularly evident when an asynchronous data source is used as the Smart IO clock.
A specific configuration leading to this issue is when the DU OpCode is set for either Shift Right or Rotate Right. If the Smart IO clock source is chosen to be from an asynchronous data line, such as a TCPWM signal, the DU load signal can be too short to be clocked in. This can result in timing errors that prevent the created project from functioning correctly.
To resolve this issue, it is important to ensure that the load signal being sent to the DU is longer than the clock period plus set up and hold times. An example of this behavior is shown in the timing diagram below. Notice that the right-shifted data is not loaded into the DU working register in the first scenario. In the second scenario, the Load pulse is clocked in and the right-shifted data is correctly loaded.