USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA - KBA222479

Version: **

 

The example project attached with this article implements UVC framework to interface an image sensor with the Host PC/mobile phone using the FX2LP device. The firmware example binds with the standard UVC driver of the Host PC/mobile phone. The firmware is tested on CY3684 EZ-USB FX2LP DVK and CrossLink LIF-MD6000 Master Link Board DVK boards. The following block diagram provides an overview of the high-level design of interfacing a camera using FX2LP and Crosslink FPGA.

Firmware features

The attached firmware uses the reference implementation of the slave FIFO interface provided with the application note AN61345  (Designing with EZ-USB® FX2LP™ Slave FIFO Interface).

The new firmware consists of slave FIFO interface and UVC framework. The UVC framework of the modified firmware is similar to that described in AN75779. Please note that this application note implements USB Video Class (UVC) Framework for an FX3 device.

The firmware supports one YUY2, 640x480 resolution. The slave FIFO interface of the FX2LP device gets the video data from the FPGA and loads it in the FX2LP’s FIFO buffer. The video data is sent to the host over the UVC interface. UVC-related requests and enumeration are handled by the FX2LP device. When FX2LP receives a video streaming request from the Host PC, the Crosslink FPGA is notified to send video data through a GPIO. Apart from GPIO and Slave FIFO control signals, the firmware does not support other control signals.

Differences in firmware between that provided with the AN61345 application note and the firmware associated with this KBA are given in the readme.txt file.

Additional Modifications Possible

You can further modify the attached firmware to include more resolutions, formats, and/or frame rates. You can also add standard UVC video controls and custom extension unit controls.

For example, if you need more resolutions with YUY2 format, you should update the descriptor file to include additional resolutions, include an I2C interface between FX2LP and FPGA (and/or image sensor) to select the resolution and update FPGA code to support additional resolutions.

Testing the Implementation

The attached project includes Crosslink FPGA code, which implements a MIPI-CSI2 Camera interface to FX2LP’s slave FIFO Master interface. The top design and the design parameter files have more details on the design architecture. There are two ways to use this project with the FX2LP device.

     1.  FPGA sends two bytes color bar/incremental color data to the FX2LP device.

     2.  FPGA gets video data from an image sensor and sends it to the FX2LP device.

You can switch from one design to another through a macro in the design parameter file. MIPI-CSI2 to parallel IP block (DPHY to CMOS) is generated for 400 MHz MIPI clock frequency, continuous clock mode, 4 data lanes and 24-bit output bus width.  When you change the image sensor configurations/switch to a different image sensor you need to update the code to match the MIPI clock frequency, number of lanes, output data format/width, etc.

Cypress has tested the color bar/incremental color data implementation on the DVK setup. See the CY3684 EZ-USB FX2LP DVK and CrossLink LIF-MD6000 Master Link Board kit guides for information on using the DVK. The following table lists the pin mappings between these two boards.

 

FX2LP slave FIFO control and data lines

CrossLink LIF-MD6000 Master Link Board

CY3684 EZ-USB FX2LP DVK

START

RX1/J2(19)

P3(19)

SYNC

RX1/J2(17)

P3(18)

SLWR

J18(9)

P2(4)

PKTEND

J18(7)

P2(13)

FIFO_EMPTY (FLAG A)

J18(3)

P2(11)

IFCLK

J18(5)

P5(3)

GND

RX2/J2(26)

P2(20)

DQ0

RX2/J2(4)

P1(19)

DQ1

RX2/J2(6)

P1(18)

DQ2

RX2/J2(10)

P1(17)

DQ3

RX2/J2(12)

P1(16)

DQ4

RX2/J2(16)

P1(15)

DQ5

RX2/J2(18)

P1(14)

DQ6

RX2/J2(11)

P1(13)

DQ7

RX2/J2(13)

P1(12)

DQ8

RX1/J2(4)

P1(11)

DQ9

RX1/J2(6)

P1(10)

DQ10

RX1/J2(10)

P1(9)

DQ11

RX1/J2(12)

P1(8)

DQ12

RX1/J2(16)

P1(7)

DQ13

RX1/J2(18)

P1(6)

DQ14

RX1/J2(11)

P1(5)

DQ15

RX1/J2(13)

P1(4)

FPGA CLOCK INPUT

J27(2)

P4(3)

 

NOTE: For pin mapping details of the Crosslink FPGA, see the .lpf file of the FPGA source code attached with this project.

Maximum USB Bandwidth Achieved

While streaming YUY2 640x480 video resolution, the maximum USB throughput achieved is 30 MBps. This is tested with e-CAMView application on a Windows10 PC and CameraFi - USB Camera / Webcam application on Android phone. You can use any third-party application that streams video from a UVC device.

Note: Cypress does not provide support for updating the Crosslink FPGA code to support additional features. Please contact Lattice Semiconductor Tech Support system to modify FPGA code. Cypress can help users update/change the FX2LP firmware design to support other features. Contact Cypress Technical Support.