How SECDED ECC Scheme Handles More Than 2-bit Errors – KBA222012

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    Translation - Japanese: SECDEC ECCスキームが2ビットを超えるエラーを処理する方法 - KBA222012 - Community Translated (JA)



    Cypress 65-nm NOR Flash has SECDED ECC, but how does it handle more than 2-bit errors?



    In Cypress 65-nm NOR Flash families, an automatic ECC scheme is implemented internally to perform Single Error Correction and Double Error Detection (SECDED). The ECC scheme is implemented with Enhanced Hamming Code that can correct 1-bit error and detect 2-bit error in one ECC page which has a size of 16 bytes in SPI NOR and 32 bytes in Parallel NOR devices.

    The following section explains how errors more than 2 bits are handled, with an introduction to the fundamentals of how the Hamming Code ECC scheme works.

    As an example, consider that two codewords are used to store the information 0 and 1. To store 0, 000 is written; to store 1, 111 is written. In this case, 000 and 111 are valid codewords. All other combinations, 001, 010, 110, … are invalid codewords, indicating that some errors have occurred.

    To decode, if the codeword is 001, it indicates that the original data is 0. If the codeword is 011, it indicates that the original data is 1.

    This shows that to change from one valid codeword to the other, from 000 to 111, 3 bits must change. In other words, this scheme has a Hamming Distance (HD) of 3.


      Figure 1 illustrates the Hamming Distance:


                             Figure 1

    The HD between Codeword A and Codeword B is 3. If a 1-bit error happens, it means that the invalid codeword is closer to A (in green circle), so it can be corrected back to A. However, if a 2-bit error happens, the decoder will mistakenly correct the code to B (in blue circle), because the invalid codeword will be closer to B.

    Therefore, with HD=3, ECC can do 1-bit correction, but not 2-bit detection or correction.

    With the same principle, if HD=4, (see the following diagram), ECC can do 1-bit correction and 2-bit detection. This is because when a 2-bit error happens, it will be on the boundary where the invalid codeword has the same distance to multiple valid codewords. The decoder knows that this is an invalid codeword but cannot determine the closest valid codeword.

    In such a scheme where HD=4, when a 3-bit error happens, it is likely that the decoder will mistakenly consider it as a 1-bit error and correct it to the closest valid codeword, resulting in a wrong correction. When a 4-bit error happens, the codeword itself may be a valid codeword to the decoder so no action may be taken.

    In Cypress 65-nm NOR devices, the SECDED ECC scheme has HD=4; therefore, if more than 2-bit errors happen, the ECC scheme will not perform a correction or may perform an incorrect action, depending on the actual errors.

    However, importantly, in these devices, the internal ECC is implemented to prevent rare cases where 1-bit soft errors may happen. It is guaranteed that during the Flash lifetime under normal usage specified in the datasheet, there will not be more than 2-bit errors in one ECC page.