PLL Clock Jitter Impact on CAN Precision in Auto MCU – KBA222406

Version 12

    Version: **

     

    Translation - Japanese: PLLクロックジッターの車載向けMCU CAN精度に対する影響 – KBA222406

     

    Question:

    When PLL clock used for a CAN peripheral, how do I verify whether the PLL clock jitter meets the CAN precision specification?

     

    Answer:

    Use the following equation to evaluate the impact of PLL Jitter on CAN precision:

    dfjitter = tjitter / (10×NBT),

    where tjitter is the specified PLL clock jitter as the absolute interval ( CAN PLL Jitter provided in product datasheet) and NBT is the Nominal Bit Time (the inverse of a given CAN bit rate). The result of  dfjitter is the drift equivalent and should be added to the oscillator drift value of the crystal or resonator:

     

    dftotal = dfjitter + dfoscillator .

     

    Here is an example to check whether the PLL clock of S6J3120 meets the CAN precision specification.

     

    Example:

    CAN bus bit rate = 500 kbps,

    CAN PLL Jitter = ±10ns  (tPJ from AC Characteristics of the S6J3120 series datasheet),

    Oscillator drift of external crystal  dfoscillator = ±0.01% (generally provided by the crystal supplier),

    Allowed CAN node frequency tolerance   df   = ±0.3%.

     

    The relative PLL Jitter interval ±10 ns results in an absolute intervaltjitter = 20ns. The 500 kbps bit rate results in NBT = (1/500 kbps) = 2 µs.

     

      dfjitter= 20ns / 10×2us = ±0.1%,

      dftotal = 0.1% + 0.01% = ±0.11% < df  = ±0.3%,

     

    Therefore, the CAN PLL Jitter spec of S6J3120 meets the CAN specification.