NAND Flash FAQs - KBA222274

Version: *E


What are the precautions to take when using NAND flash devices?


Take the following precautions when using NAND flash devices:

  • Correction by external ECC is necessary because bit corruption may occur.
  • Bad block management is necessary because block defects can occur.
  • Countermeasures are required because read disturbances will occur due to multiple read operations on the same block.
  • Wear leveling is necessary because there are restrictions on how many times a block erase can be performed.
  • Because there are restrictions on the number of multiple writes in a page, system compliance is necessary.
  • To access memory from the system, logical-physical address translation is necessary.


To handle these conditions, you should use a NAND flash controller device and NAND flash-compatible file system software.


Is the spare area usage only limited to ECC? Can it be used for file system management?

You can decide on the spare area usage. If the ECC level of the device request is secured, you can use the spare area for anything else.

For NAND flash that requires 1 bit/528 B ECC, can I use 4 bit/528 B ECC controller?

Yes. It can be used. Although this makes it go beyond the specifications, it is easy to migrate to NAND flash which requires 4 bit/(512+16) Byte in future. In addition, NAND flash devices that require 4-bit ECC cannot effectively use 1Bit/512B ECC controller because only one bit will be corrected.

What is the difference between EDC and ECC?

EDC is an error detection code while ECC is an error correction code. EDC only detects errors but does not correct errors and is built in Cypress NAND flash devices (2Gb, 4Gb) and can be used during copy back operation.

Can you ship only devices with initial bad block zero?

This is not supported.


Can I get NAND flash devices without dynamic bad block generation?

This is not supported.

How can I determine the dynamic bad block?

It depends on the file system and controller being used. For example, it is judged by failing after block erase, failing after programming, and so on.

What is read disturb?

Read disturb is the bit error that occurs when reading is repeated with NAND flash devices. Because of the cell structure, NAND flash devices stress another cell in the same block when reading a certain cell, so if the read is repeated a considerable number of times, the data gets corrupted. This is called read disturb. To avoid read disturb, it is necessary to take measures such as copying contents of pages that have frequent reads reaching a limit on to another page.

How can I recover from read disturb?

To recover from read disturb, erase the block. With a block erase, all data in the block becomes ‘1’, which cancels the effects of read disturb.

What is the multiple write limit (NOP) within a page?

NAND flash has limitations on the number of writes to the same page. The limit is 4 times/page for both 4x and 3x products. Because of the structure of the cell, NAND flash affects neighboring cells at the time of writing, so the number of writes to the same page is limited. This is called number of partial program (NOP) (Number of Partial Program). If you erase the block, this number will be reset.

What should I do if an unintended power interruption occurs and is there a possibility that the device may be damaged due to power shutdown?

A power shutdown during the time of reading will have no particular effect on the internal cell. Restart according to the Power On sequence.

If there is a power shutdown during programming (write/erase), the data of the target page/block becomes undefined. Restart according to the Power On sequence, erase again, and rewrite the correct data again.

With NAND flash, phenomena like over erase in NOR are not caused by power off during erasing. Apart from this, there is a phenomenon called over program, but it can be solved by block erase.

What is the programmer (writer) correspondence status?

See the programmer site for details.


What is Cypress' closest suggested migration path from Micron's MT29F (1-2-4 Gb) NAND Flash?

Cypress' closest suggested migration path from MT29Fxx is S34ML-1/S34ML-2 (1-2-4 Gb). However, because ML-1 is EOL, consider replacing it with ML-2 from Q3 2018 onwards. Also, because ML-2 requires 4-bit correction, there is a possibility that it cannot be replaced by a system that can only correct 1 bit.


See the following:



Is the S34ML-2 family series compatible with the Open NAND Flash Interface (ONFI) standard?


Yes. S34ML-2 products are compatible with the ONFI 1.0 specification.


What is the main difference between S34ML-1 and S34ML-2?

The spare area per page size is different. S34ML-1 has a spare area of 64B per 2 KB for all densities, while S34ML-2 has a spare area of 64B per 2 KB for 1G and 128B per 2 KB for other densities.

To migrate from S34ML-1 to S34ML-2, do I need to modify the programming files I have?

Yes. To recognize the larger spare area of S34ML-2, you will need to modify the low-level driver (LLD).

You can download the NAND LLD from the following webpage and use it as a reference for your development:


What are thermal resistance, Theta JA, Theta JB, and Theta JC of S34ML-2 devices?

Cypress does not provide theta JC and theta JB thermal resistance values for flash products. Cypress usually gives psi JT and theta JA parameters which provide a meaningful method to predict junction temperature in plastic package devices. For Theta JA and psi JT value, see the Device Qualification Report available on Cypress website.

Will the usage of the Spare Area in NAND Flash affect the endurance, data retention, or both of the memory devices?


No. The use of the spare area will not affect endurance, data retention, or both on Cypress NAND flash memory devices. In general, error correction by ECC is required for NAND. Reliability is improved if error correction of more than the error correction bit number specified in the datasheet is performed.

Does Cypress have NAND Flash with on-chip ECC?

No. Cypress does not have NAND devices with on-chip ECC. You can implement 1-bit ECC in your software for S34ML-1, and 4-bit ECC for S34ML-2.

What is wear leveling?

Wear leveling is a system measure for improving memory reliability. In flash memories including NAND, the number of erase cycles is specified for each block, and in applications that require frequent rewrite, leveling the number of erase leads to higher reliability of the device.

See Application Note: AN98521-Wear Leveling

Figure 1. Wear Leveling


What can be done to protect blocks from going bad?

There is no way to protect a block from going bad. All blocks can be a bad block potentially, and it is hard to predict when a specific block to be a bad block. But in general, minimizing program/erase count as small as possible will help to delay a block from going bad.

What is the difference between SLC NAND Flash and MLC NAND Flash?   

Single Level Cell (SLC) flash is suitable for embedded systems which require high reliability. Following are the features of SLC flash:

  • 1 bit/cell (1 bit of data is stored per cell)
  • Determines data by the presence or absence of charge Fast read, write, and erase
  • High reliability and excellent data retention characteristics


Multiple Level Cell (MLC) flash is suitable for data storage application which require large capacity. Following are the features of MLC flash:

  • 2 bit/cell (2 bits of data are stored per cell)
  • Determines data according to the amount of charge → Require more time to read, write, and erase
  • Cost benefit due to cell area reduces to half


Figure 2. SLC NAND Flash


Figure 3. MLC NAND Flash 

What operations could lead to the increase of bad blocks?

The worst usage case that could turn a block into a bad block is ‘rapid cycling’. If an application performs rapid program/erase cycling rapidly, it will lead the block to be a bad block before other blocks. For example, if a NAND file system partition has only a few remaining free blocks for ‘block replacement for a garbage collection or garbage reclamation’, then the NAND file system will rapidly perform program/erase on the same blocks.

What is the difference between the Cypress S34MS family and the Cypress S34ML family of NAND flash parts?

The main difference between the Cypress S34MS and S34ML families is S34ML has a 3.3 V power supply, whereas S34MS has a 1.8 V power supply.

How can the actual time to read cache in NAND flash be calculated?

For Read Cache operation, the first page will take longer than other pages. For example, the read time calculations for S34ML01G2 will be as follows:


Read time for first page:

Read time      = Command cycle (00h) + 5 address cycles + command cycle (30h) + tR + command cycle (31h) + tCBSYR + (Page size* tRC)

                        = 8*tRC + tR + tCBSYR + (page size*tRC)

                        = 8*25ns + 25µS + 3µS + (2112 * 25ns)

                        = 0.2µS + 25µs + 3µs + 52.8µs = ~81 (first page)


Read time for other pages:

Read time      = Command cycle (31h) + tCBSYR + (page size*tRC)

                        = 25ns + 3µS + 52.8µS = ~55.825


What is the meaning of suffix "5" in the NAND flash part number, for example S34ML02G200BHI500?

Suffix “5” in the NAND flash part number, for example S34ML02G200BHI500, indicates that the part has zero or no bad blocks.