NAND Flash FAQs - KBA222274

Version: **

What are the precautions for using NAND?

Following are some precautions for using NAND:

  • Correction by external ECC is necessary since bit corruption may occur.
  • Bad block management is necessary since block defects can occur.
  • Countermeasures are required since read disturb will occur due to multiple times read on the same block.
  • Wear leveling is necessary as there are restrictions on how many times block erase can be performed.
  • As there are restrictions on how many times multiple writing in page can be performed, system compliance is necessary.
  • To access memory from the system, logical-physical address translation is necessary.


To deal with the above, a device called NAND controller is used. Also, NAND compatible file system software is used.


Is the spare area usage only limited to ECC? Can it be used for file system management?

You can decide on the spare area usage. If the ECC level of the device request is secured, you can use the area for anything else.

For NAND that requires 1 bit/528 B ECC, can I use 4 bit/528 B ECC controller?

Yes. It can be used. Although it becomes over-specs, it is easy to migrate to NAND which requires 4 bit/(512+16) Byte in future. In addition, NAND Flash device that requires 4-bit ECC cannot effectively use 1Bit/512B ECC controller, as only one bit will be corrected.

What is the difference between EDC and ECC?

EDC is an error detection code while ECC is an error correction code. EDC only detects errors but does not correct errors and is built in Cypress NAND (2G, 4G) and can be used during copy back operation.

Can you ship only devices with initial bad block zero?

This is not supported.

I want a NAND without dynamic bad block generation.

This is not supported.

How can I determine the dynamic bad block while using the system?

It depends on the file system and controller being used. For example, it is judged by failing after block erase, failing after programming, and so on.

What is read disturb?

Bit error that occurs when reading is repeated with NAND. Because of the cell structure, NAND stresses another cell in the same block when reading a certain cell, so if the read is repeated a considerable number of times the data gets corrupted. This is called read disturb. To avoid read disturb, it is necessary to take measures such as copying pages that have increased the number of reads to a certain extent on another page.

How can I recover from read disturb?

By block erase, all data in the block becomes "1", and the effect of read disturb by read repetition is canceled.

What is the multiple write limit (NOP) within a page?

NAND has limitations on the number of write to the same page. The limit is 4 times/page for both 4x and 3x products. Because of the structure of the cell, NAND affects neighboring cells at the time of writing, so the number of writes to the same page is limited. This is called number of partial program (NOP) (Number of Partial Program). If you erase, this number will be reset.

What should I do if an unintended power interruption occurs and is there a possibility that the device may be damaged due to power shutdown?

A power shutdown during the time of reading will have no particular effect on the internal cell. Restart according to the Power On sequence. If there is a power shutdown during programming (write/erase), the data of target page/block becomes undefined. Restart according to the Power On sequence, erase again, and rewrite the correct data again. With NAND, phenomena like over erase in NOR is not caused by power off during erasing. Apart from this, there is a phenomenon called over program, but it can be solved by erase.

What is the programmer (writer) correspondence status?

See the programmer site for details.