Does the sector or chip erase time increase by age of the device?
The sector or chip erase time does not increase with age of the device, but may increase as the number of erase and program cycles increase.
What is pre-programming during erase?
During the sector or chip erase operation, pre-program refers to the operation of checking existing data bits and programming any bits from the "1" (erase) state to the "0" (program) state. When pre-programming is completed, all data bits within the memory array are pre-programmed to "0"; then the (Sector or Chip) Erase algorithm initiates, erasing all bits from the "0" (program) state to the "1" (erase) state. Flash memory can only be programmed from "1" to "0". However, Flash memory can only be (sector or chip) erased from "0" to "1" all at once for each sector or entire memory array. Within the sector or chip erase operation, the pre-program algorithm is initiated automatically, transparent to the user, and cannot be disabled.
Why does some Cypress datasheet mention "not including 00h program before erasure"?
It means that the pre-program time is not included in the erase time. For products without this remark, pre-program time is included in the erase time in the datasheet specification.
Is the write period (maximum value) in write buffer mode dependent on the number of write words?
No. Although a Flash memory device can support both single word programming and write buffer programming, the preferred method is write buffer programming as it is more efficient. However, it is recommended to load the buffer with the maximum number of words, as the write buffer time is the same whether one word or maximum words are loaded in the buffer. Therefore, the write buffer programming time does not depend on the number of words.
Is it okay to keep Byte pin open?
Do not leave the Byte pin open. Input VIL when in x8 mode, and VIH when in x16 mode. Since the GL-T series has an internal pull-up, it can be OPEN when used in x16 mode.
How can I connect byte access (how can I connect DQ15/A-1 pin to DQ14-8)?
During BYTE mode access, the DQ15 pin is assigned as A-1, the least significant bit (LSB) of the address bus. Therefore, connect A-1 pin to the lowest address A0 of the CPU. DQ14-8 will be tri-stated (high-Z) and can be left OPEN/floating. The BYTE# pin should be set "0" (LOW).
Is it okay to leave the NC pin open? Is it safe to connect the NC pin to power supply and signal wires?
Yes, NC pin can be open. The NC pin is the No Connect pin. There is no internal physical or electrical connection from the die to the lead frame. It is safe to connect the NC pin with power supply or signal wires.
What is the maximum operating junction temperature of the device?
You can obtain the junction temperature (Tj) from the following calculation.
Tj ＝ (θja × Pd) ＋ Ta
θja (℃ / W) : Thermal resistance between junction temperature (Tj) and ambient temperature (Ta)
Pd (W) : Power consumption = Operating voltage (Vd max) × Operating current (Id max)
Ta (℃) : Ambient temperature
·θja → 44 (℃ / W)
TSOP56 package, using thermal resistance value in no wind· Pd → 0.18 (W)
Use maximum power consumption (when program / erase) · Ta → 85 (℃) [Use maximum operating temperature]
Tj = (44 x 0.18) + 85 = 92.92 (℃)
It is stated in the datasheet that data retention of Flash is 20 years typ. From which point does this duration count?
Data retention of typ 20 years is the number of years from the last write on the Flash. Data retention is dependent on number of Program/Erase cycle, system field temperature, and cycling interval time. Contact Cypress for the guaranteed value of program/erase cycle and data retention.
What factors affect the data retention lifetime of the product after Program/Erase cycling?
Data retention after Program/Erase cycling is determined by three main parameters:
- System Field Temperature (Program/Erase Cycling and Data Storage)
- Total number of Program/Erase Cycles
- Cycling Interval Time
For more information on Endurance and Data Retention Characterization of Cypress Flash Memory, see AN217979.
What is the meaning of DDR in SPI Flash?
Double Date Rate (DDR) means that data can be taken on the rising and falling edges of CLK, and the data transfer speed is twice the SDR at the same CLK frequency. Cypress' FL-S, FS-S, and FL-L series support DDR features.
In the datasheet, it is shown that data retention after 10K Program/Erase and 100K Program/Erase cycles is 20 years and 2 years, respectively. What is the average field temperature for these values?
Generally, the assumption is 55 °C average temperature for data retention according to JEDEC.
What is the difference between S25FL127S and the same density S25FL128S?
FL127S is a product developed mainly for small packaging by eliminating less requested functions and adjusting its performance. For applications that require the full-feature set and higher performance, such as DDR, Vio, faster program/erase timing, and so on, it is recommended that you strongly consider S25FL128S.
What are the differences in performance between GL-T and GL-S families?
The read performance of the GL-T family is the same as the GL-S for the respective densities. The GL-S provides a high program performance of 1.5 MBps and an erase performance of 0.477 MBps compared to 1.14 MBps and 0.245 MBps, respectively, for the GL-T. The differences for each family are detailed in the application note AN202453 - Migration From GL-P and GL-S to GL-T Flash.
What is the advantage of S25FL-S over the S25FL-L family devices?
The S25FL-S family features a double-data-rate (DDR) frequency of 80 MHz compared to 66 MHz for the S25FL-L family. The S25FL-S family is, therefore, better suited for applications that require a very fast read bandwidth such as clusters and infotainment.
What is the advantage of the S25FL-L devices over the S25FL-S family devices?
The S25FL-L family features a uniform 4-KB sector architecture, whereas the S25FL-S family features 64-KB hybrid sectors and 256-KB uniform sectors. With the hybrid sector architecture, the device has a limited number of 4-KB sectors; the remaining sectors can be of 64 KB in size. The uniform 4-KB sector architecture provides greater flexibility than the hybrid sector architecture because it allows for finer granularity when programming and updating data.
Figure 1. FL-L Sector Structure
How do I reprogram the Non-volatile Configuration Register (NVCR)?
After issuing the WREN command (06h), enter the WRR (01h) command. After entering the WRR command, the device will automatically erase the register value then it programs the new value in a single operation.
For details, see the 'Write Register (WRR 01h)’ section in the device datasheet.
What is the recommended land pattern for S25FL-P, S70FL-P, S25FL-S, S70FL-S, S25FS-S, and S70FS-S family devices?
See the application note, AN98508 - Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide.
Is it better to connect to pull-up resistor when the WP#/ACC pin is not used?
The WP#/ACC pin has an internal pull-up resistor, so you can leave it open.
For Power-On Reset of S25FL1-K, if VCC drop between VCC (Min) and VCC (Low), when VCC returns, is there any problem in flash operation?
If VCC drop between VCC (min) and VCC (low) but stays above VWI, it is considered power on and will work correctly when VCC returns to the normal operating range. However, if VCC drops below VWI, you need to perform POR: for this,VCC must drop below VCC (low) for tPD period and meet the tVSL and tPUW parameters when VCC returns to the normal operating range.
Figure 2. Power-up Timing Diagram
Figure 3. Power-Down Timing Diagram
What is the difference between the lowest sector protected and the highest sector protected model?
The difference between the two models is that the protected sectors differ when WP # ACC = VIL. For the ‘High Protect’ model, the end sector will be protected. For the ‘Low Protect’ model, Sector#0 will be protected. In term of applications, there is no difference between the two models.
What is Cypress' closest suggested migration path from Micron's N25Q SPI NOR Flash?
Cypress' closest suggested migration path from N25Q is S25FL-L/S25FL-S. These may not be a direct drop-in replacement. You may need to analyze their specific situations to find out the possibility of migration. See the application note, AN202471 - Migrating to Cypress S25FL-L Serial NOR Flash from Winbond W25Q-JV/FV, Micron N25Q-A, and Macronix M25L-F Devices.
What is Cypress' closest suggested migration path from Micron's MT25QU SPI NOR Flash?
Cypress' closest suggested migration path from MT25QU is S25FS-S. These may not be a direct drop-in replacement. You may need to analyze their specific situation to find out the possibility of migration.
What is Cypress' closest suggested migration path from Micron's M29W/M29EW Parallel NOR Flash?
Cypress' closest suggested migration path from M29W/M29EW is S29GL-S. These may not be a direct drop-in replacement. You may need to analyze their specific situation to find out the possibility of migration.
What is Cypress' closest suggested migration path from Numonyx P33 Parallel NOR Flash?
Cypress' closest suggested migration path from Numonyx P33 is S29GL-S. These may not be a direct drop-in replacement. You may need to analyze their specific situation to find out the possibility of migration. See the application note, AN98584 - Migration from Numonyx™ P33 to Cypress S29GL-S.
In operating state of S29GL-S, if its temperature exceeds Ta=85℃, will it lead to destruction immediately?
Although the device will work even if it exceeds the recommended operating temperature, Cypress does not guarantee it will not cause malfunction. Also, if it exceeds its absolute maximum spec, there is a possibility of erratic operation occurring. It is essential that the device operates in its recommended operating range.
Since there is no DPD (Deep Power Down Mode) in FL-S, is there any similar function to this mode?
S25FL-S does not support any function similar to the Deep Power Down mode. Standby Power mode is the lowest power mode that consumes the lowest current. S25FL-S will enter Standby Mode and will consume ~70 µA, but it is ready to accept any command. Once the CE# input signal goes LOW, the SPI flash memory device will consume a maximum of ~100 mA.
What is the advantage of using the Write Buffer Program operation in GL series?
Each Write Buffer Program operation allows for programming of 1 bit up to 256 bytes/512 bytes. This results in faster and more effective programming time than the standard programming algorithms. Figure 4 explains how the Write Buffer Program operation in GL series devices can improve the device programming performance compared to the Single Word Programming operation.
Figure 4. Programming 256 Words to Flash
Some distributor part number has extra suffix. For example, S29AL016D70BFI020 with extra suffix E or (E). What does "E" mean?
The extra suffix was earlier used by erstwhile Spansion to represent the Fab/Assy location. After the acquisition of Spansion by Cypress, a different format is used. Create a Technical Support case to obtain the specific Fab/Assy location.