Version: **
Translation - Japanese: フラッシュデバイスのベースアドレス – KBA221223 - Community Translated (JA)
Question:
How do I define the base address of a flash memory device?
Answer:
When flash memory devices are interfaced to processors, it is necessary to define the base address of the flash chip in the system. Any base address allowed by the processor’s memory controller can be defined to be the flash base address.
Parallel NOR (PNOR), Serial NOR (SNOR), and HyperBus™ flash devices contain flash word-size storage locations that comprise an addressable memory space that can be mapped to a system address space by the processor’s memory controller. Common PNOR and HyperFlash word sizes are 16-bit (x16) or configurable 8/16-bit (x8/x16); SNOR devices on the market today are uniformly x8. The simplest case is when the system word size is equal to the flash word size – so x8 flash address and x8 system address, x16 flash address and x16 system address, and so forth. Typically, the processor’s memory controller allows the flash address space to be mapped to the system address space by writing the flash base address and flash memory size to the memory controller at system initialization time. See the following table for the starting and ending addresses in the flash address space and the system address space:
| Flash Address Space | System Address Space |
Starting Word Address | 0 | Base_address(word) |
Ending Word Address | Device_word_count(word) - 1 | Base_address(word) + Device_word_count -1 |
Here are some additional considerations when mapping a flash memory device to the system address space:
Small System Memory Window
Some PNOR memory controllers may not have enough address lines to access all locations in a high-density flash memory chip; in this case, one or more chip-enable signals from the memory controller may be used as high-order flash address lines to expand the system memory window.
Some PNOR memory controllers may have a limited system window size; in this case, the system memory window can be shifted at run-time to sample different sections of the flash address space.
Some SNOR memory controllers are limited to 3-byte (24-bit) addressing, which gives a maximum byte-addressable space of 128 Mb or 16 MB. In this case, the higher-order flash banks can be accessed by changing the bank address register on the flash device. Alternatively, 4-byte addressing can be used to access all locations in the flash device.
Flash Word Size Differs from System Word Size
For example:
- 2x8 PNOR are wired in parallel for mapping to a x16 or x32 system address space
- 2x16 PNOR are wired in parallel for mapping to a x32 system address space
- 1x8 SNOR is wired with serial 1-I/O, 2-I/O or 4-I/O for mapping to a x16 or x32 system address space
- 2x8 SNOR are wired in parallel via serial 2x1-I/O, 2x2-I/O or 2x4-I/O for mapping to a x16 or x32 system address space
- 1x16 PNOR or HyperFlash are wired normally for mapping to a x16 or x32 address space
In these cases:
- Ensure that memory controller settings and signal connections correctly map the system word address to the flash word address.
- Endianness is not an issue for read/write operations on full system words, but it is a consideration for sub-system-word read/write operations, and it is a consideration for reading little-Endian data patterns from CFI or SFDP tables factoryprogrammed by Cypress.
- Command presentation and device response byte patterns are also a consideration for multiple parallel flash memories because command patterns are sent in parallel to two distinct flash devices and response patterns may be received asynchronously from two distinct flash devices.
There are too many cases to cover all scenarios in detail here, but this article shows that correct address mapping and correct data encode/decode operations can be managed by paying attention to how your system maps the flash address space to the system address space.
