Power Loss During the Write Register (WRR) Operation in Serial NOR Flash Devices – KBA221246

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    Translation - Japanese: CypressシリアルNOR Flash Memoryのレジスタ書き換えコマンド(WRR, Write Register) フロー中の電力損失 - KBA221246 - Community Translated (JA)



    What happens if there is a sudden power loss during the Write Register operation (WRR) in Serial NOR devices?



    In the event of sudden power loss or flash reset during the Write Register operation, it is possible for the register values to become corrupted, which may change the behavior of the flash device in the system. The worst case is the system becomes nonfunctional because the flash configuration differs from the flash configuration assumed by the system. Per AN200381 - Best Practice for WRR Command for SPI Devices, the best practice is to only use the WRR command while the system is guaranteed to be running under continuous power. In practice, this means the WRR command should only be used during production programming, and it should never be used during normal system operation.


    The most common reason to use the WRR command is to turn the QUAD bit ON or OFF. If multiplexed (non-I/O) pin functions are not used, there is no harm in leaving QUAD=1 as the standard register setting – in this state, your system can use single-I/O, dual-I/O and quad-I/O at will.


    Note that the nonvolatile and one-time programmable (OTP) bit states for the Status Register and the Configuration Register are stored in a single hidden flash sector. This means that any interrupted WRR operation on the Status Register alone (8-bit WRR command), or on the Status Register and Configuration Register together (16-bit WRR command), can corrupt any nonvolatile or OTP bit within both registers. The reason is that program and erase operations on this hidden flash sector are vulnerable to interruption, just as program and erase operations on the main flash array are vulnerable to interruption. The difference is the user-level recoveries that can be used to recover interrupted operations on the main flash array cannot work on the hidden flash sector due to the additional logic that applies to the OTP bits within the registers.


    For Cypress SPI flash devices that do not also have volatile copies of the Status and Configuration registers, like the S25FL-S family, the advice given above applies. For newer Cypress SPI flash devices that have non-volatile and volatile copies of the Status and Configuration registers, the best practice given above only applies to the non-volatile registers; the system may change the volatile copies of the registers at will.