How do I enable the DPLL for a more accurate clock in PSoC Analog Coprocessor?
The TRM provides guidance, but it's easier to use the system level APIs rather than searching register lists.
Install the 32.768 kHz crystal and tuning capacitors on pins connected to P4.0 (osc in) and P4.1 (osc out).
In the start code, start the watch crystal oscillator (WCO), wait 500 msec for oscillator to settle, and then enable DPLL.
You can verify the operation by using a PWM connected to the HFClock. Connect a scope to the PWM output. At boot, the system clock is connected to the IMO, which varies slightly from the desired value. After the 500 msec delay, the PWM frequency will shift to the locked value and you can observe this in the PWM waveform.