Build CCG4M Project Using CCG4 Project in SDK 3.0.1 and Later Versions – KBA219845

Version 3

    Version: **

     

    1. Question: Does EZ-PD SDK support example projects for CCG4M part numbers?
    Answer: No

     

    2. Question: How do I build CCG4M projects using EZ-PD SDK?
    Answer: Use the CCG4 notebook project in EZ-PD SDK as a starting point and port it to the CCG4M part.

     

    3. Question: How do I customize CCG4 firmware support to CCG4M based on SDK3.0.1 onwards?
    Answer:

    1. Determine the CCG4 and CCG4M part number and pin assignment for firmware.
      CCG4M has two part numbers in the ordering information table in the CCG4M datasheet.

      Part Numbers

      To develop a CYPD4155-96BZXI project, use the CYPD4126-40LQXIT project from the EZ-PD SDK.
      To develop a CYPD4255-96BZXI project, use the CYPD4226-40LQXIT project from the EZ-PD SDK.
    2. In the firmware project, ensure that the I2C Master Component is enabled in TopDesign.cysch.
      Note: For Steps 3 and 4, you can download the datamux_ctrl.c file attached with this KBA and replace the datamux_ctrl.c file under the "solution" folder and ignore Steps 3 and 4.
    3. The USB 3.1 Gen 1/DP1.2 Mux that is internal to the CCG4M part uses the Slave Address 0x54. Change the I2C slave address assigned function in datamux_ctrl.c from 0x10 and 0x11 to 0x54.

      static const uint8_t mux_ps8740_address[NO_OF_TYPEC_PORTS] =
      {
              0x10
      #if CCG_PD_DUALPORT_ENABLE
              ,
      #endif /* CCG_PD_DUALPORT_ENABLE */
      };

      To:

      static const uint8_t mux_ps8740_address[NO_OF_TYPEC_PORTS] =
      {
             0x54
      #if CCG_PD_DUALPORT_ENABLE
             ,
             0x54
      #endif /* CCG_PD_DUALPORT_ENABLE */
      };
    4. Delete/comment all defines/functions for external SS MUX PS8742B and replace the 'Parade' portion of the code to 'Pericom' in the datamux_ctrl.c file
    5. (Additional step for CYPD4155-96BZXI only) If the target part number is CYPD4155-96BZXI, a single Type-C port design, change the target part number to CYPD4126-40LQXIT using the PSoC Creator option as follows before going to Step 6.

      a. Right-click on the project name and use Device Selector to change the part number from CYPD4126-40LQXIT to CYPD4226- 40LQXIT.

      Figure 1. Changing the Target Device with Device Seletor

    Figure 1

     

    b. Open TopDesign.cysch, and locate the Bootloadable Component. Use the bootloader binary for the CYPD4226-40LQXIT part instead of the default one, which is for CYPD4126-40LQXIT.

    Figure 2
    Figure 2

       6. Ensure that pin assignment of each GPIOs on CYPD4155-96BZXI/ CYPD4255-96BZXI device matches the real hardware design. Closely associated with the schematic is the Design Wide Resources (DWR) view, which maps each schematic element to a pin, clock, or hardware block on the CCG4 device. Open the CYPD4126-40LQXI_notebook.cydwr file to see the DWR settings for the project.

    Figure 3

    As shown in Figure 3, the DWR view has several tabs, which configure aspects such as pin mapping, interrupt mapping, clock selection, and flash security. It is recommended that you restrict any changes to the DWR to the pin mapping view. Do not change the clock, interrupt, system, or flash configurations.

    See the following table for GPIO port information versus ball location of CYPD4155-96BZXI/ CYPD4255-96BZXI

    Name

    CCG4M Ball Location

    GPIO Port

    VBUS_P_CTRL_P1

    K3

    P1_6

    VBUS_C_CTRL_P1

    K4

    P1_7

    VBUS_DISCHARGE_P1

    K8

    P2_5

    VBUS_P_CTRL_P2

    B4

    P4_2

    VBUS_C_CTRL_P2

    B5

    P4_1

    VBUS_DISCHARGE_P2

    B3

    P4_3

    VCONN_MON_P1/GPIO/VSEL_1_P1

    L7

    P2_4

    SCL_3/VCONN_MON_P2/VSEL_1_P2

    L10

    P2_7

    OVP_TRIP_P1/VSEL_2_P1

    K5

    P2_1

    OVP_TRIP_P2

    L8

    P3_0

    VBUS_MON_P1/GPIO

    L4

    P2_0

    VBUS_MON_P2

    B6

    P4_0

    HPD_P1/GPIO

    K7

    P2_3

    HPD_P2/GPIO

    E10

    P3_4

    GPIO/MUX_CTRL_3_P2

    B9

    P3_5

    GPIO/MUX_CTRL_2_P2

    B8

    P3_6

    GPIO/MUX_CTRL_1_P2

    B7

    P3_7

    VSEL_2_P2/GPIO

    H10

    P3_1

    I2C_SCL_SCB1_EC

    L6

    P0_1

    I2C_SDA_SCB1_EC

    K6

    P0_0

    I2C_INT_EC

    L5

    P2_2

    I2C_SCL_SCB2_AR/GPIO

    E2

    P1_0

    I2C_SDA_SCB2_AR/GPIO

    D2

    P1_3

    I2C_INT_AR_P1

    F2

    P1_4

    I2C_INT_AR_P2

    G2

    P1_5

    SDA_3/GPIO

    J10

    P2_6

    SCL_4

    F10

    P3_3

    SDA_4

    G10

    P3_2

    SWD_IO/AR_RST#

    B2

    P1_1

    SWD_CLK/I2C_CFG_EC

    C2

    P1_2

    7. Save all and rebuild the project.
    Two verified examples of CCG4M are available with this KBA (ccg4m_example_projects.zip).