Please note that the address pins (Ax) can be assigned in any bit order for all Asynchronous SRAMs. That means you can do the address bit assignment with any of the Address pins A[18:0] mentioned in the datasheet. Once address pin is assigned with a particular address bit, you will Read and Write from the same address. This way it does not affect the Read and Write operation. Hence, we do not provide the exact Address(A) pin numbers.
The following articles explaining this in deep and tells why some Async SRAMs do have address pins order while some don't have.
Knowledge base article - Constraints and Interchangeability of Data and Address pins in Async SRAMs: