# PSoC® 3, PSoC 4, and PSoC 5LP Analog Peripherals: Frequently Asked Questions (FAQ) - KBA219679

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Question:

Opamp

Q1: How do I calculate the bias current and offset current of PSoC opamps?

A1: For an ideal opamp, there is no current flow through the opamp’s positive and negative terminals. However, a practical opamp has bias currents called IB+ and IB-.

IB+ the current flow through the positive terminal.
IB- the current flow through the negative terminal. The bias current of PSoC opamp cannot be calculated because the PSoC GPIO leakage current is much higher than the opamp bias current. The bias current of the opamp would be several picoamperes, but the GPIO leakage current is several nanoamperes.

Because the GPIO leakage current is much higher than the bias current, the PSoC GPIO leakage current can be considered when designing the application.

The offset current is the difference between two bias currents. Considering the high GPIO leakage current, this parameter may not be significant.

Q2: What is the input impedance of a PSoC 4 opamp?

A2: The minimum input impedance of a PSoC 4 opamp is 35 MΩ. The analog front ends of comparator (CTBm-based comparator) and opamp are same. Thus, opamp input impedance is the same as the comparator input impedance, which is 35 MΩ as specified in comparator datasheet.

Q3: Can you provide the magnitude plot of the PSoC 4 opamp?

A3: The magnitude plot can be drawn using the open loop gain and the gain-bandwidth product of opamp. The opamp gain-bandwidth product varies based on the opamp power. Values of the gain-bandwidth product for different power levels are provided below: The open loop bandwidth is calculated based on the gain-bandwidth product and the open-loop gain (approximately equal to 31623) The magnitude plot is given here: Because PSoC opamps are unity-gain compensated, the opamp response looks like a first-order system when the frequency is less than the unity gain bandwidth (gain-bandwidth product).

Q4: How do I achieve the gain of more than 1000 using a PSoC opamp?

A4: The opamp gain-bandwidth product limits the maximum gain achieved for the given input bandwidth. To achieve the required gain, the input frequency should be much less than the opamp’s closed-loop bandwidth. If the input has both DC offset and AC signal, it is possible that the DC offset might saturate the opamp because of the higher gain in the single stage. To get the AC signal with a higher gain by eliminating the DC offset, a multistage amplifier can be used. The high-pass filter between each amplifier stage removes the DC offset.

The resultant gain of the multistage circuit is calculated as shown below:

Total gain = Amplifier gain 1 * Amplifier gain 2 *....* Amplifier gain N

N is the amplifier stages.

Q5: Is there any SPICE model available for PSoC opamps?

A5: No. There is no SPICE model available for PSoC opamps.

Q6: How do I realize active filters using PSoC opamps?

A6: It is possible to realize the active filters using a PSoC opamp with external resistors and capacitors. Some of the filter topologies are mentioned in the following knowledge base articles:

DAC

Q1: What is the maximum resolution achieved by PSoC 4 Parallel IDACs?

A1: The maximum resolution achieved by PSoC 4 parallel IDACs is 9-bits. Table 1 explains the over lapping range of the 8-bit IDAC and 7-bit IDAC for the 9-bit IDAC. By using an 8-bit IDAC with a step size of 2.4 µA, it is possible to achieve the 614-µA full range. Similarly, by using a 7-bit IDAC with a step of 1.2 µA, it is possible to achieve 153.6 µA. By combining both 8-bit and 7-bit IDAC, it is possible to achieve a 9-bit resolution. Table 1 explains the 9-bit IDAC ranges that could be achieved by combining an 8-bit IDAC and a 7-bit IDAC. Therefore, for 9-bit IDAC data, the eight MSB bits should be written at the 8-bit IDAC, and the LSB (0th bit) should be written as the 0 th bit of the 7-bit IDAC. Because the gain error, offset error, and nonlinearity errors are different for two IDACs, the overall performance of the Parallel IDAC would be less than that of individual IDACs.

See AN64275 - PSoC® 3 and PSoC 5LP: Getting More Resolution from 8-Bit DACs for more information.

Note that the methods described in the application note are applicable for PSoC 4 family device also.

Q2: The maximum VDAC voltage in PSoC 3/PSoC 5LP is limited to about VDDA–1V, due to the IDAC compliance voltage. Is there a way to increase the VDAC voltage above this?

The VDAC can be cascaded with a programmable gain amplifier (PGA) referred to internal Vss and with a Gain > 1, as shown in the sample below: However, this method has several limitations such as the following:

•

All VDAC codes would not be possible. Because only a few integer PGA gain values are available, the VDAC codes above a certain value would result in saturation of the PGA output.

You may choose the VDAC range and PGA gain based on VDDA:
For example, if VDDA = 3.3 V, use the VDAC range = 0 – 1.020 V, PGA Gain = 4
For VDDA = 5.0 V, use the VDAC range = 0 – 4.080 V, PGA Gain = 2
• In addition, the output of the PGA also may not rise up to VDDA. The output swing of the PGA is limited to about 150 mV from the rails (both VDDA and VSSA).

Q1: Why is the conversion rate of PSoC 4 SAR ADC different from the expected formula when hardware trigger is used?

The expected conversion rate = (acquisition time + resolution + 2) clock cycles A1: This is expected behavior. The conversion time is more than the expected value when hardware trigger is used, because SOF and EOF are routed through the Digital Signal Interconnect (DSI) routing and these signals encounter a delay, resulting in longer conversion time. The actual conversion time will be 4-5 clock cycles more than the expected conversion time when hardware trigger is used.

Q2: What is the meaning of actual conversion rate in PSoC SAR ADC configuration window and why is this value not the same as the desired conversion rate?

A2: This is the limitation of clock dividers available in the PSoC device. PSoC has integer clock dividers. The ADC clock is derived based on IMO/integer clock divider. If the clock divider does not provide the expected ADC clock frequency, the actual and the desired clock frequency will be different.

To avoid this, the IMO can be changed to achieve the desired clock frequency.

Ensure that the IMO value is at least two times higher than the ADC clock frequency.

The following snapshot shows the difference in values of desired clock frequency and actual clock frequency. This difference is because the IMO is 48 MHz, and by using an integer divider, the closest frequency obtainable is 16 MHz. The following snapshot illustrates the actual settings in the .cydwr window. The closest ADC clock frequency achievable from an IMO of 48 MHz is 16 MHz. In this example, to achieve the 18-MHz ADC clock frequency as the actual frequency, open the cydwr tab and go to Clock > Edit Clock, and change the IMO value to 36 MHz. The settings should be as shown below: Now, it would be possible to get the actual ADC clock frequency as desired. The following snapshot shows the same value in the desired clock frequency and the actual clock frequency. Q3: Which are the 16 channels that PSoC 4200M and PSoC 4200L SAR ADC can support?

A3: The 16 single-ended channels mentioned in the datasheets do not provide direct GPIO support for the SAR ADC.

The SAR ADC in PSoC 4200M and PSoC 4200L supports eight dedicated channels that do not use AMuxBus. This is controlled by the SAR Mux bus. The following snapshot shows the eight dedicated channels for the SAR ADC in PSoC 4200BLE/ PSoC 4200M/ PSoC 4200L devices. The two channels are from AMUXBUS. The followingsnap shot shows how P0 and P0 are connected to the SAR ADC through AMuxBus. Because there are four opamps, it is possible to connect four additional GPIOs to SAR ADC through the opamps. The following snapshot shows how opamps are used to connect the four inputs to the SAR ADC. Die temp is connected to a dedicated INJ channel.

One duplicated pin from GPIO. Here, Pin_8 is the “duplicated GPIO pin”.

The resultant top design looks as shown below: Q4: Is it possible to use separate ISR for each interrupt source of SAR ADC?

A4: No, it is not possible to use a separate ISR for each interrupt of SAR ADC. SAR ADC has multiple interrupt requests such as End of Conversion (EOC), overflow, limit detect, and collision. However, all SAR ADC interrupts have the same ISR. From the above diagram, it is clear that multiple interrupt sources are combined to generate the single sar_interrupt hardware request. Therefore, a single ISR is used to service multiple SAR ADC interrupts. To find the individual interrupt source, it is required to check each bit of ADC_SAR_INTR_REG separately in the ISR.

Q5: In PSoC 4100/4200, is it possible to output Vref (through the Vref bypass pin) while the device is in Deep Sleep?

No, it is not possible to have the Vref pin powered during deep sleep because the SAR reference buffer is turned OFF during deep sleep.

Q6: In PSoC 4, can the Vref voltage bypassed on the “Vref bypass pin” of the SAR ADC be used to drive an external circuit?

No, the Vref bypass pin is intended to reduce the noise on the internal Vref; it should not be loaded by external circuits. Therefore, if Vref is required for external circuits that do not offer high impedance, Vref must be buffered by an opamp buffer before feeding it to external circuits (an opamp voltage follower in PSoC can be used).

Q7: Is the input impedance of PSoC 4 SAR ADC as low as 2.2 kΩ?

No, the 2.2 kΩ resistor mentioned as Rin would not appear between the input pin to ground. It just comes in the path between the input pin to the sampling capacitor (10 pF) at the SAR ADC's input as shown in the diagram below..

Based on the sampling rate used for the SAR ADC, this 10-pF capacitor would need to get charged that many times each second. The impedance seen by the source,

Rin = 1/ (10 pF * sample rate)

Therefore, the impedance changes based on the sample rate. See the application note, AN88619 - PSoC 4 Hardware Design Considerations (refer to page 17) for a detailed explanation of the configuration of the acquisition time, taking into account the source impedance of the input.

Q1: Does the DelSig buffer gain affect the INL and DNL of DelSig ADC?

A1: The buffer gain does not affect the integral nonlinearity (INL) and differential nonlinearity (DNL) of the DelSig ADC. The DelSig block has two parts: buffer and DelSig core. The gain error, offset error, and nonlinearity errors, which are mentioned in the datasheet are for the DelSig core block. The change in buffer gain may affect the gain and offset error of the DelSig ADC, but does not affect the INL and DNL of the ADC.

Analog Routing

Q1: How do I manually route GPIO pin to analog blocks in a PSoC 4 family device?

Background: Because of the routing restrictions in PSoC Creator, some routings that are usually allowed in PSoC device cannot be implemented in PSoC Creator during compile time. For example, consider the following case. It is required to scan 9 inputs of which 7 inputs are scanned continuously. Two inputs need not be scanned continuously so it is planned to use the AMuxBus to switch between two inputs. The resultant top design looks like: P2_3 and P0_7 are connected through AMux_1 to SAR Mux bus. Even though this routing seems to be viable in PSoC, PSoC Creator does not allow this because of limitations in routing algorithms.

To make this routing feasible, route the P0_7 to SAR Mux bus using firmware. This section explains how to route the GPIO to SAR ADC in firmware using registers. For simplicity, SAR ADC with only one channel is considered. Consider the top design shown below, where P0_7 needs to be connected to the SAR ADC input where P2_3 is already connected. The analog editor window looks as follows: It is clear that P2_3 is connected to the SAR Mux bus Vplus pin and P0_7 needs to be connected the SAR Mux bus. Therefore, do the following to route P0_7 to the SAR Mux vplus pin:

1.

Disconnect P2_3 from the SAR Mux bus by using the SAR_MUX_SWITCH_CLEAR0 register. See the PSoC 4200 Register TRM: http://www.cypress.com/file/136296/download for details.

CY_SET_XTND_REG32((void CYFAR *)CYREG_SAR_MUX_SWITCH_CLEAR0,
CY_GET_XTND_REG32(CYREG_SAR_MUX_SWITCH_CLEAR0) | (0x1 << CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET));

In this command, P2_3 is cleared from the SAR Mux bus.

2.

Connect AMUXBUS A or AMUXBUS B to the SAR Mux Bus vplus terminal by using the SAR_MUX_SWITCH0 register. Here, the SAR ADC Mux is connected to AMUXBUS A.

CY_SET_XTND_REG32((void CYFAR *)CYREG_SAR_MUX_SWITCH0,
CY_GET_XTND_REG32(CYREG_SAR_MUX_SWITCH0) | (0x1 <<
CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET));
3.

Finally, connect P0_7 to AMUXBUS A using the CYREG_HSIOM_PORT_SEL0 register.

CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x60000000u);

Copy these commands and paste them in the main.c file. After executing these commands in main.c, the resultant Analog device editor looks like this: However, even though the Analog editor window shows what is expected, the result will not be correct because DSI routing is not enabled while routing the GPIO to the SAR Mux bus.

When a GPIO is connected to any analog blocks in top design, DSI is automatically enabled. However, when GPIO is connected to analog blocks by using firmware, DSI is not automatically enabled. Do the following to enable DSI in this case. Double-click the Pin_2 to open the configuration window. Along with analog type, the digital output also should be checked and Drive mode should be set as “High impedance analog”. This is explained in the above snapshot.

The two more terminals appear in top design. This should be connected to the “logic 1” block. The resultant top design looks like this: This will help to get the expected output using SAR ADC.

Application-specific queries

Q1: How do I implement a 4-20mA current loop using PSoC?

A1: It is possible to implement a 4-20mA current loop using PSoC and a single external transistor. See the article "Just Add a Transistor: The 4-20 mA Current Loop" in planetanalog.com.

Q2: How do I measure the battery voltage using PSoC?

A2: See the PSoC Hacker article:
http://www.cypress.com/blog/psoc-hacker-blog/measuring-vdd-battery-volts-psoc4

Q3: How do I measure current using PSoC?

A3: If the current is less than a few milliamps, the Transimpedance amplifier (TIA) can be used to measure the current. The schematic of the TIA is attached here: Rf is the external feedback resistor. A PSoC opamp can be used to convert the input current into voltage. Here, the photodiode acts as the current source.

If the input is an AC signal, the feedback capacitor is used to reduce the high-frequency noise and limit the bandwidth of the input signal. If the current is more than several milliamperes, current sensing resistors are used to sense the current. There are two types of current sensing to sense the power supply current: Low-side current sensing and High-side current sensing Q4: How do I measure a negative voltage in PSoC?

PSoC 1:
See the Cypress blog: http://www.cypress.com/blog/psoc-hacker-blog/measuring-negative-voltage-using-psoc1 PSoC 3/PSoC 4/PSoC 5LP devices do not have an AGND. However, a similar buffered reference voltage can be generated using the internal opamps in these devices; this signal can serve the purpose of AGND as used for PSoC 1 device described in the blog.

PSoC 3/PSoC 5LP:
AGND can be generated by using a Vref Component and then buffering it using an opamp configured as a voltage follower: PSoC 4:
AGND can be generated by using an opamp as a voltage follower, but the reference can be derived using by either using an external resistive divider or the SAR Vref bypass pin. The two options are illustrated below.

External resistive divider method: Note that a pin Pin_1 can be used instead of ground to save current in low-power modes. This Pin_1 can be configured to “Open/drain drives low” drive mode, and set to '0' when measurements are to be made;, set to '1' at other times.

SAR Vref bypass method: Q5: How do I protect the PSoC device from any potential high-voltage events on GPIO pins?

The absolute maximum voltage allowed on PSoC GPIO pins is 0.5 V above the GPIO pin supply or 0.5 V below ground. If there is any chance of the input voltage to exceed this, it is recommended to protect the PSoC device by using a series resistor and Schottky diode arrangement as shown in the following diagram. The diodes D_1 and D_2 are low forward drop Schottky diodes such as the NSR05F20NXT5G Schottky Barrier Diode from ON Semiconductor. See the datasheet at https://www.onsemi.com/pub/Collateral/NSR05F20.PDF

A R_3 resistor value of 100 Ω will keep the voltage on the GPIO pin below ± 0.4 V (over VDD/below Gnd) for Vinput values up to ± 50 V. Therefore, the PSoC device will remain unaffected because it can stand voltages up to ± 0.5 V (over VDD/below Gnd) on its GPIO pins.

Q6: Can a voltage be applied to PSoC 3/PSoC 4/PSoC 5LP GPIO pins when the device is not powered?

No, the voltage applied on GPIO pins can power up the device through the ESD diode present in the GPIO pin. The current rating on the ESD diodes is about 100 µA.

If there is any possibility in your system for voltage to appear on an un-powered PSoC device’s GPIO pin, that signal can be connected to PSoC as shown below: SIO pins in PSoC 3/PSoC 5LP devices and OVT pins in certain PSoC 4 devices do not have these ESD diodes to VDDD/VDDIO, and therefore, applying a voltage on these pins when the device is not powered does not create issues. This voltage should be within the maximum voltage supported on the pins.

Q7: How do I dynamically change the amplitude and frequency of WaveDAC in firmware?

• The frequency of the generated wave can be changed dynamically by using the "External Clock" option in the WaveDAC Component and connecting a clock Component to it. In the clock Component, select "New" clock. You can change the clock's frequency in firmware using the Clock_SetDivider() API. The changing of this clock frequency would result in change in the generated sine wave.
• The amplitude can be changed by cascading the WaveDAC Component with a programmable gain amplifier (PGA) Component. Because the PGA's gain can be changed in firmware using the PGA_SetGain() API, the amplitude of the final output (output of PGA) can be controlled.

The following sample schematic illustrates this. Notes:

• You should set the amplitude of the WaveDAC wave to the minimum amplitude required in the application, because the PGA cannot provide gains less than 1. For higher amplitudes, the PGA gain can be raised above 1 in firmware.
• The PGA's reference voltage should be same as the offset voltage of the WaveDAC wave so that the wave would be amplified symmetrically about the offset voltage. For this offset, you can use a VDAC Component, and set it to the same value as WaveDAC offset (e.g., 2.040 V). In addition, this VDAC should be buffered by an opamp follower because the VDAC output impedance is not low (1K or 4K) and the PGA's reference terminal would load it.
• This recommendation might impose some limitations on the amplitudes possible, based on the PGA gain. For more flexibility, you may need to implement the signal chain completely using VDAC, DMA, and flash look-up table containing sine wave sample values. The look-up table can be scaled in amplitude, or different look-up tables can be used for different amplitudes.

Troubleshooting Guide

Q1: IDAC does not output the required current.

Is it ensured that the output of the IDAC is connected to a voltage lower than the “VDDA - Idac compliance voltage”?

This is required for the IDAC to operate correctly.

Q2: When using the VDDA range for ADC in a kit, why does the ADC output reported by CountsTomV (or uV) API have a large error compared to input voltage?

The VDDA voltage on kits may not be exactly 5 V due to drops across Schottky diodes feeding the regulator, or the tolerance of the regulator.

To reduce this error, measure the actual VDDA in the kit using a multimeter and enter this value in the VDDA field of the System tab (as shown in the following screenshot). This value is used as a reference by the CountsTomV(or uV) API to compute the result from the counts. Q3: When a PSoC 4 SAR ADC is used in single-ended mode, why is the resolution only 11-bit, not 12-bit? Is it possible to measure 0-VDDA with 12-bit resolution?

The ADC is actually a differential ADC, with half of its range occurring when the negative input is greater than the positive input. If used in single-ended mode and the single-ended negative input is "Vss", the negative half of the range cannot be used because the positive terminal cannot go below Vss.

For further details, see “Single ended result format” in PSoC4 SAR ADC Component datasheet

To measure 0-VDDA with 12-bit resolution, use the following settings:

Vref = VDDA/2 (bypass, if required)
Single ended negative input = Vref

Single Ended Result format = Unsigned 