Yes, there are. It is mentioned in Note 3 of the CY7B991/2, CY7B9911 datasheets; and Note 11 of the CY7B9910/20datasheet.
When the FS pin is selected HIGH, the REF input must not transition upon power-up until Vcc has reached 4.3V. As the power supply ramps-up, the PLL "wakes up" before the output buffers. Since the output buffers are not yet functional, there are no transitions on the FB. The PLL thinks that it is not running fast enough, so it speeds up, eventually reaching its maximum allowable rate as dictated by the FS pin. Finally, Vcc reaches the level where the output buffers become functional. When FS pin is HIHG, it is possible for the internal VCO to run faster than the outputs can follow (only undivided outputs can exhibit this behavior). Although the outputs are functional, they still cannot provide the proper transitions on the FB and thus, the PLL still "thinks" that it is running too slow. The end result is that the VCO locks up at its maximum rate and stays there with the outputs not able to provide the proper transitions.