- What design considerations are there when depth cascading multiple CY7C4231 FIFOs?
- What needs to be done with the flags when depth cascading?
Applications often require FIFO buffers deeper than those offered by discrete devices. By depth expanding multiple devices, a logically deeper FIFO can be constructed. The synchronous FIFO family offers two approaches to this common application. The CY7C42x1 family of x9 devices does not contain on-chip expansion circuitry, so another method of setting up this system is available.
These synchronous FIFOs do not have on-chip expansion circuitry. Instead, there are two write enable and two read enable signals (each with a different polarity) to allow a "ping-pong" arrangement. So if we are depth cascading 4 FIFOs, on the first write operation, we would write to one FIFO, then the next write cycle we would switch to the second FIFO, then to the third, and then the fourth. After writing to the fourth FIFO on the fourth write cycle, we would move back to the first FIFO for the fifth write cycle. This arrangement allows the use of the /PAE and /PAF signals as well as the /EF and /FF signals. This is because when any of the individual programmable flags are set off, the overall state of all four FIFOs is comparably almost empty/full. The only disadvantage of this design is that there is a little loss in the maximum speed of this system as the databus must switch every clock cycle.
The read/write enables are used to enable only one FIFO at a time. For this design to work there needs to be some external read and write enable controller. This controller would be responsible for switching /WEN1, WEN2, /REN1, and /REN2.